公开(公告)号：US20220037266A1

公开(公告)日：2022-02-03

申请号：US16944102

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Shih-Ting Lin ,  Szu-Wei Lu ,  Chen-Hsuan Tsai ,  I-Ting Huang

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48

Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The semiconductor device is disposed on the second surface of the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is directly in contact with the insulating encapsulation.

公开(公告)号：US11101252B2

公开(公告)日：2021-08-24

申请号：US16548817

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ting Lin ,  Chin-Fu Kao ,  Jing-Cheng Lin ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2

公开(公告)号：US11101145B2

公开(公告)日：2021-08-24

申请号：US16177576

申请日：2018-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Chen-Hsuan Tsai ,  Chung-Chieh Ting ,  Shih-Ting Lin ,  Szu-Wei Lu

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate, a die stacking unit, a number of dummy micro bumps, and an underfill material. The die stacking unit, which is mounted on the base substrate, includes a first die, a second die, and a number of first conductive joints. The first die and the second die are stacked on each other, and the first conductive joints are disposed between and connected to the first die and the second die. The dummy micro bumps, which are disposed between the first conductive joints, are connected to the first die but not to the second die. The underfill material is filled into a number of gaps between the base substrate, the first die, the second die, the first conductive joints, and the dummy micro bumps.

公开(公告)号：US10923438B2

公开(公告)日：2021-02-16

申请号：US16396001

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Kung-Chen Yeh ,  I-Ting Huang ,  Shih-Ting Lin ,  Szu-Wei Lu

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/544 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00 ,  H01L25/18

Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.

公开(公告)号：US20180366439A1

公开(公告)日：2018-12-20

申请号：US15627458

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Tsung-Fu Tsai ,  Chen-Hua Yu ,  Po-Hao Tsai ,  Shih-Ting Lin ,  Szu-Wei Lu ,  Hung-Wei Tsai ,  Chen-Hsuan Tsai

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

公开(公告)号：US10157888B1

公开(公告)日：2018-12-18

申请号：US15627458

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Tsung-Fu Tsai ,  Chen-Hua Yu ,  Po-Hao Tsai ,  Shih-Ting Lin ,  Szu-Wei Lu ,  Hung-Wei Tsai ,  Chen-Hsuan Tsai

IPC: H01L21/68 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/66 ,  H01L25/10 ,  H01L21/683

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

公开(公告)号：US11205629B2

公开(公告)日：2021-12-21

申请号：US16843876

申请日：2020-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Shih-Ting Lin ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48

Abstract: A package structure including a wiring substrate, conductive terminals, an insulating encapsulation, a redistribution circuit structure, guiding patterns and a semiconductor device. The conductive terminals are disposed on a surface of the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate and the conductive terminals. The redistribution circuit structure is disposed on the insulating encapsulation and the conductive terminals, and the redistribution circuit structure is electrically connected to the wiring substrate through the conductive terminals. The guiding patterns are disposed between the wiring substrate and the redistribution circuit structure, and the guiding patterns are in contact with and encapsulated by the insulating encapsulation. The semiconductor device is disposed on a top surface of the redistribution circuit structure, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure and the conductive terminals.

公开(公告)号：US11133289B2

公开(公告)日：2021-09-28

申请号：US16414723

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Shih-Ting Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78

Abstract: A semiconductor package includes a first integrated circuit structure, a second integrated circuit structure, a plurality of conductive bumps, an encapsulating material, and a redistribution structure. The first integrated circuit structure includes an active surface having a plurality of contact pads, a back surface opposite to the active surface, and a plurality of through vias extending through the first integrated circuit structure and connecting the active surface and the back surface. The second integrated circuit structure is disposed on the back surface of the first integrated circuit structure. The conductive bumps are disposed between the first integrated circuit structure and the second integrated circuit structure, and electrically connecting the plurality of through vias and the second integrated circuit structure. The encapsulating material at least encapsulates the second integrated circuit structure. The redistribution structure is disposed over and electrically connected to the active surface of the first integrated circuit structure.

公开(公告)号：US20210225791A1

公开(公告)日：2021-07-22

申请号：US16843876

申请日：2020-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Shih-Ting Lin ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48

Abstract: A package structure including a wiring substrate, conductive terminals, an insulating encapsulation, a redistribution circuit structure, guiding patterns and a semiconductor device. The conductive terminals are disposed on a surface of the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate and the conductive terminals. The redistribution circuit structure is disposed on the insulating encapsulation and the conductive terminals, and the redistribution circuit structure is electrically connected to the wiring substrate through the conductive terminals. The guiding patterns are disposed between the wiring substrate and the redistribution circuit structure, and the guiding patterns are in contact with and encapsulated by the insulating encapsulation. The semiconductor device is disposed on a top surface of the redistribution circuit structure, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure and the conductive terminals.

公开(公告)号：US20210193577A1

公开(公告)日：2021-06-24

申请号：US16718219

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ting Lin ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

Abstract: Package structure and method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge die, and a second encapsulant. The first encapsulant laterally encapsulates the first die and the second die. The bridge die is electrically connected to the first die and the second die. The second encapsulant is located over the first die, the second die and the first encapsulant, laterally encapsulating the bridge die and filling a space between the bridge die and the first die, between the bridge die and the first encapsulant and between the bridge die and the second die. A material of the second encapsulant is different from a material of the first encapsulant.