公开(公告)号：US20240297166A1

公开(公告)日：2024-09-05

申请号：US18664483

申请日：2024-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US11978720B2

公开(公告)日：2024-05-07

申请号：US17347871

申请日：2021-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai Jun Zhan ,  Chin-Fu Kao ,  Kuang-Chun Lee ,  Ming-Da Cheng ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/16 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81203

Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

公开(公告)号：US11450654B2

公开(公告)日：2022-09-20

申请号：US16925326

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Chin-Fu Kao ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L21/50 ,  H01L25/18

Abstract: A package structure includes a circuits substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.

公开(公告)号：US11302683B2

公开(公告)日：2022-04-12

申请号：US16836927

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Pan ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/56 ,  G02B6/13 ,  H01L23/24

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure.

公开(公告)号：US11296051B2

公开(公告)日：2022-04-05

申请号：US16547609

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Fu Kao ,  Chih-Yuan Chien ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.

公开(公告)号：US11239134B2

公开(公告)日：2022-02-01

申请号：US16745338

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

公开(公告)号：US20210118758A1

公开(公告)日：2021-04-22

申请号：US16655135

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Chin-Fu Kao ,  Szu-Wei Lu ,  Chih-Chien Pan

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: Semiconductor packages and methods of forming the same are disclosed. a semiconductor package includes a die and an underfill. The die is disposed over a surface and includes a first sidewall. The underfill encapsulates the die. The underfill includes a first underfill fillet on the first sidewall, and in a cross-sectional view, a second sidewall of the first underfill fillet has a turning point.

公开(公告)号：US20210057384A1

公开(公告)日：2021-02-25

申请号：US16547609

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Fu Kao ,  Chih-Yuan Chien ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.

公开(公告)号：US20200212006A1

公开(公告)日：2020-07-02

申请号：US16234568

申请日：2018-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hua Chang ,  Chin-Fu Kao

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/528 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A package contact structure, a semiconductor package and a manufacturing method are provided. The package contact structure includes a conductive feature and a dielectric barrier. The conductive feature includes a first portion and a second portion disposed on the first portion. Materials of the first portion and the second portion are different. The dielectric barrier is sleeved on the first portion and extends to cover at least a part of the second portion. A maximum height of the dielectric barrier is less than a maximum height of the conductive feature.

公开(公告)号：US20200020633A1

公开(公告)日：2020-01-16

申请号：US16035693

申请日：2018-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hua Chang ,  Chin-Fu Kao

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56

Abstract: A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure.