公开(公告)号：US11961919B2

公开(公告)日：2024-04-16

申请号：US17699477

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chung Chang ,  Hsiu-Hao Tsao ,  Ming-Jhe Sie ,  Shun-Hui Yang ,  Chen-Huang Huang ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

公开(公告)号：US20240321581A1

公开(公告)日：2024-09-26

申请号：US18360447

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ging Lin ,  Shun-Hui Yang ,  Yen Ju Chen ,  Yun-Chen Wu ,  Chun-Liang Lai

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a first fin and around first channel regions that are disposed over the first fin; forming an interlayer dielectric (ILD) layer over the first fin around the dummy gate structure; replacing the dummy gate structure with a gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the first fin, where the first and second dielectric plugs cut the gate structure into a plurality of segments separated from each other; removing a segment of the gate structure interposed between the first dielectric plug and the second dielectric plugs to expose the first channel regions; removing the exposed first channel regions, where after removing the exposed first channel regions, a recess is formed in the ILD layer; and filling the recess with a dielectric material.

公开(公告)号：US20220209023A1

公开(公告)日：2022-06-30

申请号：US17699477

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chung Chang ,  Hsiu-Hao Tsao ,  Ming-Jhe Sie ,  Shun-Hui Yang ,  Chen-Huang Huang ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.