公开(公告)号：US20230027789A1

公开(公告)日：2023-01-26

申请号：US17730797

申请日：2022-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Wei Yin ,  Yun-Chen Wu ,  Tzu-Wen Pan ,  Jih-Sheng Yang ,  Yu-Hsien Lin ,  Ryan Chia-Jen Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

Abstract: Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.

公开(公告)号：US20250126841A1

公开(公告)日：2025-04-17

申请号：US18591792

申请日：2024-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ging Lin ,  Chun-Liang Lai ,  Yun-Chen Wu

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A structure includes a plurality of semiconductor regions, a first gate stack and a second gate stack immediately neighboring each other, a first fin isolation region in the first gate stack, and a second fin isolation region in the second gate stack. The first fin isolation region and the second fin isolation region have a sideway overlap having an overlap distance being equal to or greater than a pitch of the plurality of semiconductor regions. The overlap distance is measured in a direction parallel to lengthwise directions of the first gate stack and the second gate stack. A plurality of source/drain regions are on opposing sides of the first gate stack and the second gate stack to form a plurality of transistors.

公开(公告)号：US20240321581A1

公开(公告)日：2024-09-26

申请号：US18360447

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ging Lin ,  Shun-Hui Yang ,  Yen Ju Chen ,  Yun-Chen Wu ,  Chun-Liang Lai

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a first fin and around first channel regions that are disposed over the first fin; forming an interlayer dielectric (ILD) layer over the first fin around the dummy gate structure; replacing the dummy gate structure with a gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the first fin, where the first and second dielectric plugs cut the gate structure into a plurality of segments separated from each other; removing a segment of the gate structure interposed between the first dielectric plug and the second dielectric plugs to expose the first channel regions; removing the exposed first channel regions, where after removing the exposed first channel regions, a recess is formed in the ILD layer; and filling the recess with a dielectric material.