公开(公告)号：US20250087633A1

公开(公告)日：2025-03-13

申请号：US18520414

申请日：2023-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Ting Hao Kuo ,  Chen-Shien Chen ,  Chih-Sheng Li

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00

Abstract: A device includes a package component including an interconnect structure on a first side of a substrate; metal pads on the interconnect structure; a semiconductor die connected to a second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package component and over the dielectric material; a first buffer layer over the passivation layer, wherein the first buffer layer extends over the package component and over the dielectric material, wherein a width of the first buffer layer is greater than a width of the package component and is less than a width of the passivation layer; and conductive connectors penetrating the passivation layer and the first buffer layer to physically contact the metal pads.

公开(公告)号：US20250105084A1

公开(公告)日：2025-03-27

申请号：US18530102

申请日：2023-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chen-Shien Chen ,  Ting Hao Kuo ,  Jen-Yuan Chang

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes forming a dummy component, including: forming through-substrate vias (TSVs) in a substrate; forming a thermal structure over the TSVs, wherein the thermal structure includes metal lines in dielectric layers; forming a bonding layer over the thermal structure; and forming bond pads within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component.

公开(公告)号：US20240112924A1

公开(公告)日：2024-04-04

申请号：US18150256

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Hsien Chen ,  Chen-Shien Chen ,  Ting Hao Kuo ,  Chi-Yen Lin ,  Yu-Chih Huang

IPC: H01L21/56 ,  H01L21/306 ,  H01L21/768 ,  H01L21/78 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/563 ,  H01L21/30604 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/5389

Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.

公开(公告)号：US20250014961A1

公开(公告)日：2025-01-09

申请号：US18404243

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hong Wang ,  Chen-Shien Chen ,  Ting Hao Kuo ,  Yu-Chia Lai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: Gap-fill dielectrics for die structures and methods of forming the same are provided. In an embodiment, a device includes: an outer gap-fill dielectric having a first coefficient of thermal expansion; a first integrated circuit die in the outer gap-fill dielectric; a second integrated circuit die in the outer gap-fill dielectric; an inner gap-fill dielectric between the first integrated circuit die and the second integrated circuit die, the inner gap-fill dielectric having a second coefficient of thermal expansion, the second coefficient of thermal expansion being greater than the first coefficient of thermal expansion; and a third integrated circuit die over the inner gap-fill dielectric, the third integrated circuit die bonded to the first integrated circuit die and to the second integrated circuit die.

公开(公告)号：US20220367420A1

公开(公告)日：2022-11-17

申请号：US17874598

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chi-Hui Lai ,  Ting Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/40 ,  H01L23/367

Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

公开(公告)号：US20240304535A1

公开(公告)日：2024-09-12

申请号：US18334695

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting Hao Kuo ,  Hui-Chun Chiang ,  Yu-Chia Lai

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76829 ,  H01L24/06 ,  H01L2224/05025

Abstract: A device includes: a first integrated circuit (IC) die; a first dielectric material around first sidewalls of the first IC die; a second IC die over and electrically coupled to the first IC die; and a second dielectric material over the first dielectric material and around second sidewalls of the second IC die, where in a top view, the second sidewalls of the second IC die are disposed within, and are spaced apart from, the first sidewalls of the first IC die.