公开(公告)号：US20150162334A1

公开(公告)日：2015-06-11

申请号：US14624782

申请日：2015-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jon-Hsu HO ,  Chih-Ching WANG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Chih-Chieh YEH ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract translation: 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。

公开(公告)号：US20150249141A1

公开(公告)日：2015-09-03

申请号：US14672298

申请日：2015-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsing YU ,  Chia-Wen LIU ,  Ken-Ichi GOTO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51 ,  H01L29/16 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833 ,  Y10S438/931

Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract translation: 提供晶体管和形成晶体管的方法。 该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。 使用具有低倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。 晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。 掺杂剂分布在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域。

公开(公告)号：US20140103438A1

公开(公告)日：2014-04-17

申请号：US14108391

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching WANG ,  Jon-Hsu HO ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L29/78

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

Abstract translation: 一种多栅半导体器件及其制造方法。 形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。 第一晶体管具有第一掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。 第二晶体管具有第二掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

公开(公告)号：US20150194485A1

公开(公告)日：2015-07-09

申请号：US14661237

申请日：2015-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mahaveer Sathaiya DHANYAKUMAR ,  Wei-Hao WU ,  Tsung-Hsing YU ,  Chia-Wen LIU ,  Tzer-Min SHEN ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/26586 ,  H01L21/76232 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract translation: 设置在浅沟槽隔离（STI）结构之间的MOSFET包括形成在衬底表面上并在STI结构的向内延伸的突出部上延伸的外延硅层。 因此，MOSFET的栅极宽度是外延硅层的宽度，并且大于STI结构之间的原始衬底表面的宽度。 外延硅层形成在预先掺杂的沟道上，并且在沉积时未被掺杂。 可以使用热激活操作来将掺杂剂杂质驱动到由外延硅层占据的晶体管沟道区域中，但是外延硅层与栅极电介质相交的沟道位置处的掺杂剂浓度最小化。