公开(公告)号：US11527713B2

公开(公告)日：2022-12-13

申请号：US16921133

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bi-Shen Lee ,  Hai-Dang Trinh ,  Hsun-Chung Kuang ,  Tzu-Chung Tsai ,  Yao-Wen Chang

IPC: H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

公开(公告)号：US20210242399A1

公开(公告)日：2021-08-05

申请号：US16921133

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bi-Shen Lee ,  Hai-Dang Trinh ,  Hsun-Chung Kuang ,  Tzu-Chung Tsai ,  Yao-Wen Chang

IPC: H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

公开(公告)号：US20210066591A1

公开(公告)日：2021-03-04

申请号：US16807564

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Hsing-Lien Lin ,  Tzu-Chung Tsai ,  Fa-Shen Jiang ,  Bi-Shen Lee

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

公开(公告)号：US11024774B2

公开(公告)日：2021-06-01

申请号：US16601822

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Chang ,  Tzu-Chung Tsai ,  Yen-Chang Chu ,  Chia-Hua Lin

IPC: H01L33/40 ,  H01L51/52

Abstract: Various embodiments of the present disclosure are directed towards a display device. The display device includes an isolation structure disposed over a semiconductor substrate. An electrode is disposed at least partially over the isolation structure. A light-emitting structure is disposed over the electrode. A conductive reflector is disposed below the isolation structure and electrically coupled to the electrode. The conductive reflector is disposed at least partially between sidewalls of the light-emitting structure. The conductive reflector comprises a non-metal-doped aluminum material.

公开(公告)号：US20210066587A1

公开(公告)日：2021-03-04

申请号：US16788611

申请日：2020-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Tzu-Chung Tsai ,  Fa-Shen Jiang

IPC: H01L45/00

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

公开(公告)号：US11131025B2

公开(公告)日：2021-09-28

申请号：US16907714

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Tsai ,  Chii-Ming Wu ,  Hai-Dang Trinh

IPC: C23C16/52 ,  H01L21/67 ,  H04N5/232 ,  C23C16/455 ,  C23C14/34 ,  G06T7/00 ,  C23C14/54 ,  C23C14/52 ,  G06T7/80

Abstract: In some embodiments, the present disclosure relates to a process tool which includes a housing that defines a vacuum chamber. A wafer chuck is in the housing, and a carrier wafer is on the wafer chuck. A structure that is used for deposition processes is arranged at a top of the housing. A camera is integrated on the wafer chuck such that the camera faces a top of the housing. The camera is configured to wirelessly capture images of the structure used for deposition processes within the housing. Outside of the housing is a wireless receiver. The wireless receiver is configured to receive the images from the camera while the vacuum chamber is sealed.

公开(公告)号：US20210111312A1

公开(公告)日：2021-04-15

申请号：US16601822

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Chang ,  Tzu-Chung Tsai ,  Yen-Chang Chu ,  Chia-Hua Lin

IPC: H01L33/40 ,  H01L51/52

Abstract: Various embodiments of the present disclosure are directed towards a display device. The display device includes an isolation structure disposed over a semiconductor substrate. An electrode is disposed at least partially over the isolation structure. A light-emitting structure is disposed over the electrode. A conductive reflector is disposed below the isolation structure and electrically coupled to the electrode. The conductive reflector is disposed at least partially between sidewalls of the light-emitting structure. The conductive reflector comprises a non-metal-doped aluminum material.

公开(公告)号：US11881421B2

公开(公告)日：2024-01-23

申请号：US17216247

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Tsai ,  Ping-Cheng Ko ,  Fang-yu Liu ,  Jhih-Yuan Yang

IPC: H01L21/673 ,  B29C45/72 ,  B29C45/73 ,  B29C45/74 ,  B29C45/78 ,  B29C35/16 ,  B29L31/00 ,  B29K69/00

CPC classification number: H01L21/67386 ,  B29C45/7207 ,  B29C45/73 ,  B29C45/74 ,  B29C45/78 ,  H01L21/67366 ,  H01L21/67369 ,  H01L21/67373 ,  H01L21/67396 ,  B29C2035/1616 ,  B29C2945/76531 ,  B29C2945/76668 ,  B29C2945/76688 ,  B29C2945/76765 ,  B29K2069/00 ,  B29L2031/712

Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.

公开(公告)号：US11309491B2

公开(公告)日：2022-04-19

申请号：US16788611

申请日：2020-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Tzu-Chung Tsai ,  Fa-Shen Jiang

IPC: H01L45/00

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

公开(公告)号：US20210098398A1

公开(公告)日：2021-04-01

申请号：US16589497

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Julie Yang ,  Chii-Ming Wu ,  Tzu-Chung Tsai ,  Yao-Wen Chang

IPC: H01L23/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.