公开(公告)号：US20200152757A1

公开(公告)日：2020-05-14

申请号：US16741381

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi LEE ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG ,  Chia-Sheng FAN

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/84 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.

公开(公告)号：US20180004882A1

公开(公告)日：2018-01-04

申请号：US15197026

申请日：2016-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Heng HSIEH ,  Bao-Ru YOUNG ,  Yu-Jung CHANG ,  Tzung-Chi LEE

IPC: G06F17/50 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L29/6681 ,  H01L29/7851

Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

公开(公告)号：US20180331199A1

公开(公告)日：2018-11-15

申请号：US16044227

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi LEE ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG ,  Chia-Sheng FAN

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/84

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.

公开(公告)号：US20180182859A1

公开(公告)日：2018-06-28

申请号：US15649865

申请日：2017-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi LEE ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG ,  Chia-Sheng FAN

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.

公开(公告)号：US20180137232A1

公开(公告)日：2018-05-17

申请号：US15854358

申请日：2017-12-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Heng HSIEH ,  Tzung-Chi LEE ,  Yu-Jung CHANG ,  Bao-Ru YOUNG

IPC: G06F17/50 ,  H01L29/78 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L29/6681 ,  H01L29/7851

Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.