公开(公告)号：US20180182859A1

公开(公告)日：2018-06-28

申请号：US15649865

申请日：2017-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi LEE ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG ,  Chia-Sheng FAN

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.

公开(公告)号：US20180137232A1

公开(公告)日：2018-05-17

申请号：US15854358

申请日：2017-12-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Heng HSIEH ,  Tzung-Chi LEE ,  Yu-Jung CHANG ,  Bao-Ru YOUNG

IPC: G06F17/50 ,  H01L29/78 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L29/6681 ,  H01L29/7851

Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

公开(公告)号：US20220059524A1

公开(公告)日：2022-02-24

申请号：US16996986

申请日：2020-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chia HSU ,  Tung-Heng HSIEH ,  Yung-Feng CHANG ,  Bao-Ru YOUNG ,  Jam-Wem LEE ,  Chih-Hung WANG

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers and the second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. Each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.

公开(公告)号：US20180337053A1

公开(公告)日：2018-11-22

申请号：US15599045

申请日：2017-05-18

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Yi-Jyun HUANG ,  Bao-Ru YOUNG ,  Tung-Heng HSIEH

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49

Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.

公开(公告)号：US20180004882A1

公开(公告)日：2018-01-04

申请号：US15197026

申请日：2016-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Heng HSIEH ,  Bao-Ru YOUNG ,  Yu-Jung CHANG ,  Tzung-Chi LEE

IPC: G06F17/50 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L29/6681 ,  H01L29/7851

Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

公开(公告)号：US20170154966A1

公开(公告)日：2017-06-01

申请号：US15157274

申请日：2016-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jyun HUANG ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/41791 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.

公开(公告)号：US20210082769A1

公开(公告)日：2021-03-18

申请号：US17093350

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Sheng FAN ,  Chun-Yen LIN ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG

IPC: H01L21/8234 ,  H01L29/66

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

公开(公告)号：US20230187277A1

公开(公告)日：2023-06-15

申请号：US18162841

申请日：2023-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung WANG ,  Bao-Ru YOUNG ,  Tung-Heng HSIEH

IPC: H01L21/768 ,  G06F30/39 ,  G06F30/398 ,  H01L21/66 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L21/76892 ,  G06F30/39 ,  G06F30/398 ,  H01L21/76895 ,  H01L22/20 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2027/11881

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having a first pattern layer that includes first source/drain (S/D) contacts and second S/D contacts, the first and second S/D contacts are spaced away from each other by a spacing along a first direction, and each of the first and second S/D contacts have elongated shapes extending lengthwise in a second direction perpendicular to the first direction. The method includes constructing a conductive feature on a second pattern layer of the IC layout, the conductive feature having an initial rectangular shape with a length and a width, the length extending along the first direction. And the method includes modifying the conductive feature to form a modified conductive feature that is overlapped with the first S/D contacts and distanced away from the second S/D contacts.

公开(公告)号：US20200152757A1

公开(公告)日：2020-05-14

申请号：US16741381

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi LEE ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG ,  Chia-Sheng FAN

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/84 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.

公开(公告)号：US20190259664A1

公开(公告)日：2019-08-22

申请号：US16397938

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Sheng FAN ,  Chun-Yen LIN ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG

IPC: H01L21/8234

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.