公开(公告)号：US20190305107A1

公开(公告)日：2019-10-03

申请号：US15939389

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju CHEN ,  Su-Hao LIU ,  Chun-Hao KUNG ,  Liang-Yin CHEN ,  Huicheng CHANG ,  Kei-Wei CHEN ,  Hui-Chi HUANG ,  Kao-Feng LIAO ,  Chih-Hung CHEN ,  Jie-Huang HUANG ,  Lun-Kuang TAN ,  Wei-Ming YOU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.

公开(公告)号：US20200020544A1

公开(公告)日：2020-01-16

申请号：US16035159

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Ming CHANG ,  Chih-Cheng LIN ,  Chi-Ying WU ,  Wei-Ming YOU ,  Ziwei FANG ,  Huang-Lin CHAO

IPC: H01L21/322 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165

Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

公开(公告)号：US20170133509A1

公开(公告)日：2017-05-11

申请号：US15415790

申请日：2017-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ting HSIAO ,  Cheng-Ta WU ,  Lun-Kuang TAN ,  Liang-Yu YEN ,  Ting-Chun WANG ,  Tsung-Han WU ,  Wei-Ming YOU

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.