公开(公告)号：US11467488B2

公开(公告)日：2022-10-11

申请号：US16441158

申请日：2019-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen Lo ,  Shih-Ming Chang ,  Chun-Hung Liu

IPC: G03F1/78 ,  H01J37/09 ,  H01J37/317 ,  H01J37/10

Abstract: A method of operating a semiconductor apparatus includes forming a first electron beam passing through a first shaping aperture; modifying an energy distribution of the first electron beam by a second shaping aperture, such that the first electron beam has a main region and an edge region having a greater energy than the main region; and exposing a workpiece to the main region and the edge region of the first electron beam to create a pattern.

公开(公告)号：US11054748B2

公开(公告)日：2021-07-06

申请号：US16138402

申请日：2018-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

公开(公告)号：US20200098545A1

公开(公告)日：2020-03-26

申请号：US16138402

申请日：2018-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

IPC: H01J37/317 ,  H01J37/302 ,  G03F7/20 ,  G03F1/78

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

公开(公告)号：US11556058B2

公开(公告)日：2023-01-17

申请号：US16664425

申请日：2019-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen Lo ,  Shih-Ming Chang

IPC: H01J37/317 ,  H01J37/304 ,  G03F7/20

Abstract: A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.

公开(公告)号：US11526081B2

公开(公告)日：2022-12-13

申请号：US17366319

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

公开(公告)号：US20210405534A1

公开(公告)日：2021-12-30

申请号：US17366319

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

IPC: G03F7/20 ,  G03F1/36

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

公开(公告)号：US11899367B2

公开(公告)日：2024-02-13

申请号：US18064548

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78

CPC classification number: G03F7/2061 ,  G03F1/36 ,  G03F1/78

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

公开(公告)号：US20230273524A1

公开(公告)日：2023-08-31

申请号：US18064548

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

IPC: G03F7/20 ,  G03F1/36

CPC classification number: G03F7/2061 ,  G03F1/36 ,  G03F1/78

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

公开(公告)号：US20180164688A1

公开(公告)日：2018-06-14

申请号：US15378442

申请日：2016-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Wen Lo

IPC: G03F7/20

CPC classification number: G03F7/2059 ,  G03F7/70425 ,  G03F7/70558

Abstract: Systems and methods are disclosed herein for enhancing lithography printability, and in particular, for enhancing image contrast. An exemplary method includes receiving an integrated circuit (IC) design layout and generating an exposure map based on the IC design layout. The IC design layout includes a target pattern to be formed on a workpiece, and the exposure map includes an exposure grid divided into dark pixels and bright pixels that combine to form the target pattern. The method further includes adjusting the exposure map to increase exposure dosage at edges of the target pattern. In some implementations, the adjusting includes locating an edge portion of the target pattern in the exposure map, where the edge portion has a corresponding bright pixel, and assigning exposure energy from at least one dark pixel to the corresponding bright pixel, thereby generating a modified exposure map.

公开(公告)号：US11543753B2

公开(公告)日：2023-01-03

申请号：US16886509

申请日：2020-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Wen Lo ,  Wei-Shuo Su ,  Hua-Tai Lin

IPC: G03F7/20

Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.