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公开(公告)号：US11467488B2
公开(公告)日：2022-10-11
申请号：US16441158
申请日：2019-06-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wen Lo , Shih-Ming Chang , Chun-Hung Liu
IPC: G03F1/78 , H01J37/09 , H01J37/317 , H01J37/10
Abstract: A method of operating a semiconductor apparatus includes forming a first electron beam passing through a first shaping aperture; modifying an energy distribution of the first electron beam by a second shaping aperture, such that the first electron beam has a main region and an edge region having a greater energy than the main region; and exposing a workpiece to the main region and the edge region of the first electron beam to create a pattern.
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公开(公告)号：US11054748B2
公开(公告)日：2021-07-06
申请号：US16138402
申请日：2018-09-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
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公开(公告)号：US20200098545A1
公开(公告)日：2020-03-26
申请号：US16138402
申请日：2018-09-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
IPC: H01J37/317 , H01J37/302 , G03F7/20 , G03F1/78
Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
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Patent Agency Ranking
公开(公告)号：US11526081B2
公开(公告)日：2022-12-13
申请号：US17366319
申请日：2021-07-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
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公开(公告)号：US20210405534A1
公开(公告)日：2021-12-30
申请号：US17366319
申请日：2021-07-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
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公开(公告)号：US11899367B2
公开(公告)日：2024-02-13
申请号：US18064548
申请日：2022-12-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
CPC classification number: G03F7/2061 , G03F1/36 , G03F1/78
Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
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公开(公告)号：US20230273524A1
公开(公告)日：2023-08-31
申请号：US18064548
申请日：2022-12-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
CPC classification number: G03F7/2061 , G03F1/36 , G03F1/78
Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
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公开(公告)号：US09418049B2
公开(公告)日：2016-08-16
申请号：US13742881
申请日：2013-01-16
Inventor： Kuen-Yu Tsai , Chun-Hung Liu
CPC classification number: G06F17/18 , G03F1/70 , G03F7/70433 , G03F7/705 , H01J37/00 , H01J37/3174 , H01J2237/31761 , H01J2237/31762
Abstract: A method for establishing a parametric model of a semiconductor process is provided. A first intermediate result is generated according to layout data and a non-parametric model of the semiconductor process. A first response is obtained according to the first intermediate result. A specific mathematical function is selected from a plurality of mathematical functions, and the parametric model is obtained according to the specific mathematical function. A second intermediate result is generated according to the layout data and the parametric model. A second response is obtained according to the second intermediate result. It is determined whether the parametric model is an optimal model according to the first and second responses.
Abstract translation: 提供了一种用于建立半导体工艺的参数模型的方法。 根据布局数据和半导体工艺的非参数模型生成第一中间结果。 根据第一中间结果获得第一响应。 从多个数学函数中选择具体的数学函数，并且根据具体的数学函数获得参数模型。 根据布局数据和参数模型生成第二个中间结果。 根据第二中间结果获得第二响应。 根据第一和第二响应确定参数模型是否是最优模型。
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