公开(公告)号：US20240387501A1

公开(公告)日：2024-11-21

申请号：US18782354

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong Chern ,  Yi-An Lai

IPC: H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

公开(公告)号：US20230154912A1

公开(公告)日：2023-05-18

申请号：US17650758

申请日：2022-02-11

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chan-Hong Chern ,  Yi-An Lai

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/83047 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1425

Abstract: A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

公开(公告)号：US20240274555A1

公开(公告)日：2024-08-15

申请号：US18313746

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Syun-Ming Jang ,  Ming-Hsing Tsai ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ya-Lien Lee ,  Chih-Han Tseng ,  Chih-Cheng Kuo ,  Yi-An Lai ,  Kevin Huang ,  Kuan-Hung Ho

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/0239 ,  H01L2224/0384 ,  H01L2224/05073 ,  H01L2224/05184 ,  H01L2224/05582

Abstract: Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.

公开(公告)号：US20250087533A1

公开(公告)日：2025-03-13

申请号：US18619626

申请日：2024-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsing Tsai ,  Ya-Lien Lee ,  Chih-Han Tseng ,  Kuei-Wen Huang ,  Kuan-Hung Ho ,  Ming-Uei Hung ,  Chih-Cheng Kuo ,  Yi-An Lai ,  Wei-Ting Chen

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.