公开(公告)号：US20240006234A1

公开(公告)日：2024-01-04

申请号：US18364286

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/7681 ,  H01L23/53238 ,  H01L23/5226 ,  H01L21/76879

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US11837500B2

公开(公告)日：2023-12-05

申请号：US17809919

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/7681 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US11527476B2

公开(公告)日：2022-12-13

申请号：US17143496

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Min Liu ,  Chia-Pang Kuo ,  Chien Chung Huang ,  Chih-Yi Chang ,  Ya-Lien Lee ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.

公开(公告)号：US20220328347A1

公开(公告)日：2022-10-13

申请号：US17809919

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US20190027404A1

公开(公告)日：2019-01-24

申请号：US16130183

申请日：2018-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Lien Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01J37/32 ,  H01L23/522 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/02

Abstract: A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the diffusion barrier layer in a second chamber. The clean chamber is configured to reduce overhangs in the copper seed layer by producing a plasma comprising positively and negatively charged ions including halogen ions, filtering the plasma to selectively exclude positively charged ions, and bombarding with the filtered plasma. The tool and related method can be used to reduce overhangs and improve subsequent gap fill while avoiding excessive damage to the dielectric matrix.

公开(公告)号：US08962473B2

公开(公告)日：2015-02-24

申请号：US13833794

申请日：2013-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Shiang Kuo ,  Ken-Yu Chang ,  Ya-Lien Lee ,  Hung-Wen Su

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.

Abstract translation: 在制造半导体器件的方法中，在半导体衬底之上的电介质层的内部形成有开口。 开口有一堵墙。 然后通过至少两个交替的步骤在开口的壁上形成至少一个扩散阻挡材料，所述至少两个交替步骤选自由物理气相沉积（PVD）和原子层沉积（ALD）的过程组成的组。 衬里层形成在至少一个扩散阻挡材料上。

公开(公告)号：US20250087533A1

公开(公告)日：2025-03-13

申请号：US18619626

申请日：2024-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsing Tsai ,  Ya-Lien Lee ,  Chih-Han Tseng ,  Kuei-Wen Huang ,  Kuan-Hung Ho ,  Ming-Uei Hung ,  Chih-Cheng Kuo ,  Yi-An Lai ,  Wei-Ting Chen

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.

公开(公告)号：US11527411B2

公开(公告)日：2022-12-13

申请号：US17372650

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rueijer Lin ,  Ya-Lien Lee ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/285 ,  H01L21/768

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

公开(公告)号：US20210287994A1

公开(公告)日：2021-09-16

申请号：US16814116

申请日：2020-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Chii-Ping Chen ,  Neng-Jye Yang ,  Ya-Lien Lee ,  An-Jiao Fu ,  Ya-Ching Tseng

IPC: H01L23/532 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.

公开(公告)号：US09812397B2

公开(公告)日：2017-11-07

申请号：US14587019

申请日：2014-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Shiang Kuo ,  Ken-Yu Chang ,  Ya-Lien Lee ,  Hung-Wen Su

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.