公开(公告)号：US20200152576A1

公开(公告)日：2020-05-14

申请号：US16741001

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Da TSAI ,  Cheng-Ping LIN ,  Wei-Hung LIN ,  Chih-Wei LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48

Abstract: Package structures and methods for forming the same are provided. The method includes forming a redistribution structure embedded in a passivation layer over a carrier substrate and bonding an integrated circuit die to the redistribution structure through first connectors. The method further includes removing the carrier substrate to expose a bottom portion of the redistribution structure and removing the bottom portion of the redistribution structure to form an opening in the passivation layer. The method further includes forming a second connector over the redistribution structure. In addition, the second connector includes an extending portion extending into the opening in the passivation layer.

公开(公告)号：US20180308800A1

公开(公告)日：2018-10-25

申请号：US16020030

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Da TSAI ,  Cheng-Ping LIN ,  Wei-Hung LIN ,  Chih-Wei LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L23/31

Abstract: Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.

公开(公告)号：US20180130749A1

公开(公告)日：2018-05-10

申请号：US15347912

申请日：2016-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da TSAI ,  Cheng-Ping LIN ,  Wei-Hung LIN ,  Chih-Wei LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/29

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5386 ,  H01L24/17 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/3511

Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.