公开(公告)号：US12021037B2

公开(公告)日：2024-06-25

申请号：US18077778

申请日：2022-12-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/5386 ,  H01L24/17 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/81815 ,  H01L2924/00014

摘要： Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.

公开(公告)号：US11961810B2

公开(公告)日：2024-04-16

申请号：US17352844

申请日：2021-06-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Wei Lin ,  Sheng-Yu Wu ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13166 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81444 ,  H01L2924/00014 ,  H01L2224/81439 ,  H01L2924/00014 ,  H01L2224/81424 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2224/13116 ,  H01L2924/014 ,  H01L2224/13686 ,  H01L2924/05432 ,  H01L2224/13686 ,  H01L2924/053 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/13005 ,  H01L2924/206 ,  H01L2224/13005 ,  H01L2924/207

摘要： An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

公开(公告)号：US20240113090A1

公开(公告)日：2024-04-04

申请号：US17958007

申请日：2022-09-30

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Won Myoung KI ,  In Su MOK ,  Soo Hyun KIM ,  Tae Kyeong HWANG ,  Shaun BOWERS ,  George SCOTT

IPC分类号： H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/16 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3185 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/18161 ,  H01L2924/19103

摘要： In one example, an electronic device includes an electronic component including a component first side, a component second side opposite to the component first side, and a component lateral side connecting the component first side to the component second side, wherein the component lateral side defines a perimeter of the electronic component. A first intermediate terminal is coupled to the electronic component within the perimeter. An intermediate component is coupled to the first intermediate terminal within the perimeter. An encapsulant structure is over the intermediate component, at least a portion of the first intermediate terminal, and at least a portion of the electronic component. Other examples and related methods are also disclosed herein.

公开(公告)号：US20240105530A1

公开(公告)日：2024-03-28

申请号：US18151040

申请日：2023-01-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wensen Hung ,  Tsung-Yu Chen

IPC分类号： H01L23/10 ,  H01L23/00 ,  H01L23/36 ,  H01L23/42 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/10 ,  H01L23/36 ,  H01L23/42 ,  H01L23/562 ,  H01L24/29 ,  H01L24/32 ,  H01L25/18 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204

摘要： In an embodiment, a device includes: an integrated circuit package including: a package component; and a package stiffener attached to the package component; and a heat spreader attached to the integrated circuit package, a main portion of the heat spreader disposed above the package stiffener, a protruding portion of the heat spreader extending through the package stiffener; an elastic adhesive material between the main portion of the heat spreader and the package stiffener; and a thermal interface material between the protruding portion of the heat spreader and the package component, the thermal interface material different from the elastic adhesive material.

公开(公告)号：US20240071998A1

公开(公告)日：2024-02-29

申请号：US17893354

申请日：2022-08-23

申请人： Taiwan Semiconductor Manufacturing Company

发明人： Li-Hsien Huang ,  Hsueh-Lung Cheng ,  Yao-Chun Chuang ,  Yinlung Lu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L25/0655 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/96 ,  H01L25/18 ,  H01L2224/05073 ,  H01L2224/05555 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06134 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16258 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2224/96

摘要： A method of packaging a semiconductor includes: positioning first and second semiconductor dies by one another on a carrier substrate, wherein first and second zones zone are defined with respect to the first die and third and fourth zones are defined with respect to the second die; forming first vias in the first zone, the first vias having a first size; forming second vias in the second zone, the second vias having a second size different from the first; forming third vias in the third zone, the third vias having a third size; forming fourth vias in the fourth zone, the fourth vias having a fourth size different from the third; and electrically connecting the first and second dies with an interconnection die such that electrical signals are exchangeable therebetween.

公开(公告)号：US11908819B2

公开(公告)日：2024-02-20

申请号：US18046134

申请日：2022-10-12

申请人： Apple Inc.

发明人： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/498 ,  H01L24/11 ,  H01L24/13 ,  H01L24/25 ,  H01L24/26 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/11003 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14517 ,  H01L2224/16112 ,  H01L2224/24996 ,  H01L2224/2501 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/73204 ,  H01L2224/83051

摘要： Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US11901325B2

公开(公告)日：2024-02-13

申请号：US15543113

申请日：2016-01-13

申请人： DEXERIALS CORPORATION

发明人： Seiichiro Shinohara ,  Yasushi Akutsu ,  Tomoyuki Ishimatsu

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/27 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/32 ,  H01L2224/111 ,  H01L2224/11003 ,  H01L2224/131 ,  H01L2224/133 ,  H01L2224/1308 ,  H01L2224/1319 ,  H01L2224/1369 ,  H01L2224/13078 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13686 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17107 ,  H01L2224/271 ,  H01L2224/27003 ,  H01L2224/27515 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29082 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81101 ,  H01L2224/81122 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83122 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00015 ,  H01L2924/3841 ,  H01L2924/00015 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/83203 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/81122 ,  H01L2924/00012 ,  H01L2224/83122 ,  H01L2924/00012 ,  H01L2224/271 ,  H01L2924/00012 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13157 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2224/133 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0635 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/2929 ,  H01L2924/0635 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29387 ,  H01L2924/05442 ,  H01L2224/29387 ,  H01L2924/05432 ,  H01L2224/29387 ,  H01L2924/00012 ,  H01L2224/1319 ,  H01L2924/00014 ,  H01L2224/111 ,  H01L2924/00012 ,  H01L2224/1369 ,  H01L2924/00014 ,  H01L2224/13686 ,  H01L2924/00014

摘要： Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having a plated film formed in the inner surface. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are selectively present at a position where the through holes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through holes are connected by the conductive particles, and the semiconductor substrates each having the through hole are bonded by an insulating adhesive.

公开(公告)号：US11770982B1

公开(公告)日：2023-09-26

申请号：US17397015

申请日：2021-08-09

申请人： Rigetti & Co, LLC

发明人： Jayss Daniel Marshall ,  Chih-Yang Li ,  Biswajit Sur ,  Nagesh Vodrahalli ,  Mehrnoosh Vahidpour ,  William Austin O'Brien, IV ,  Andrew Joseph Bestwick ,  Chad Tyler Rigetti ,  James Russell Renzas

IPC分类号： H10N60/80 ,  H01L23/00 ,  G06N10/00 ,  H10N60/85 ,  H10N60/01

CPC分类号： H10N60/805 ,  G06N10/00 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H10N60/0156 ,  H10N60/0912 ,  H10N60/85 ,  H01L2224/1146 ,  H01L2224/11452 ,  H01L2224/1318 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13179 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/1432

摘要： In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.

公开(公告)号：US11728297B2

公开(公告)日：2023-08-15

申请号：US17325384

申请日：2021-05-20

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/05 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L23/3128 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0362 ,  H01L2224/03416 ,  H01L2224/03418 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03831 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05085 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/1312 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8181 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2224/05171 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13118 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13116 ,  H01L2924/013 ,  H01L2924/00014

摘要： A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

公开(公告)号：US20230238344A1

公开(公告)日：2023-07-27

申请号：US17888915

申请日：2022-08-16

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

发明人： Tomohiro SAITO

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13109 ,  H01L2224/13184 ,  H01L2224/13166 ,  H01L2224/13164 ,  H01L2224/13188 ,  H01L2224/16145 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/04941 ,  H01L2924/1306 ,  H01L2924/1461 ,  H01L2924/1436 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2224/81193 ,  H01L2224/81201

摘要： An electronic device includes a first structure body and a second structure body. The first structure body includes a first base body, a first bonding electrode and a first hard part. The second structure body includes a second base body, and a second bonding electrode. The first bonding electrode and the second bonding electrode are bonded to each other between the first base body and the second base body. The first hard part is located between the first base body and the second base body. The first hard part is positioned within an area in which the first bonding electrode is located when viewed along a first direction. The first direction is from the first base body toward the first bonding electrode. The first hard part has a higher hardness than the first bonding electrode.