公开(公告)号：US20180233382A1

公开(公告)日：2018-08-16

申请号：US15952509

申请日：2018-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shing-Chao CHEN ,  Chih-Wei LIN ,  Meng-Tse CHEN ,  Hui-Min HUANG ,  Ming-Da CHENG ,  Kuo-Lung PAN ,  Wei-Sen CHANG ,  Tin-Hao KUO ,  Hao-Yi TSAI

IPC: H01L21/56 ,  H01L23/58 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/566 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/585 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/81

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.

公开(公告)号：US20180090561A1

公开(公告)日：2018-03-29

申请号：US15830979

申请日：2017-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20170154954A1

公开(公告)日：2017-06-01

申请号：US14954524

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20230275048A1

公开(公告)日：2023-08-31

申请号：US18312325

申请日：2023-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hao CHENG ,  Yen-Yu CHEN ,  Chih-Wei LIN ,  Yi-Ming DAI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L24/03 ,  H01L24/08 ,  H01L23/3171 ,  H01L21/56 ,  H01L21/76888 ,  H01L21/76802 ,  H01L23/5226

Abstract: A method is provided. The method includes forming an interconnect structure electrically connected to a semiconductor device; forming a tantalum-based barrier layer over the interconnect structure; oxidizing the tantalum-based barrier layer to form a tantalum oxide over the tantalum-based barrier layer; and forming a metal layer over the tantalum oxide.

公开(公告)号：US20200294944A1

公开(公告)日：2020-09-17

申请号：US16888758

申请日：2020-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

公开(公告)号：US20180342514A1

公开(公告)日：2018-11-29

申请号：US16055526

申请日：2018-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO ,  Cheng-Wei LIAN

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

Abstract: Methods for forming a semiconductor structure are provided. The method includes forming a first dummy gate structure and forming first spacers over a sidewall of the first dummy gate structure. The method includes removing the first dummy gate structure to form a first trench between the first spacers and forming a first capping layer in the first trench. A first portion of the first capping layer covers a sidewall of the first trench and a second portion of the first capping layer covers a bottom surface of the first trench. The method further includes oxidizing a sidewall of the first portion of the first capping layer and a top surface of the second portion of the first capping layer to form a first capping oxide layer and forming a first work function metal layer and forming a first gate electrode layer over the first work function metal layer.

公开(公告)号：US20180286823A1

公开(公告)日：2018-10-04

申请号：US15726260

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31

Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.

公开(公告)号：US20240290734A1

公开(公告)日：2024-08-29

申请号：US18655596

申请日：2024-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L23/3128 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/12105

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

公开(公告)号：US20220165689A1

公开(公告)日：2022-05-26

申请号：US17670481

申请日：2022-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

公开(公告)号：US20200075518A1

公开(公告)日：2020-03-05

申请号：US16430075

申请日：2019-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hao CHENG ,  Yen-Yu CHEN ,  Chih-Wei LIN ,  Yi-Ming DAI

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56

Abstract: A method for forming a bond pad structure includes forming an interconnect structure on a semiconductor device, forming a passivation layer on the interconnect structure, forming at least one opening through the passivation layer, forming an oxidation layer at least in the opening, and forming a pad metal layer on the oxidation layer. A portion of the interconnect structure is exposed by the at least one opening.