公开(公告)号：US20150116686A1

公开(公告)日：2015-04-30

申请号：US14066949

申请日：2013-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Yao LEE ,  Ying-Ying WANG ,  Yi-Ping HSIEH ,  Heng-Hsin LIU

IPC: G03F9/00

CPC classification number: G03F9/7084 ,  G03F9/70 ,  G03F9/7007 ,  G03F9/7046 ,  G03F9/7088 ,  G03F2009/005

Abstract: An edge-dominant alignment method for use in an exposure scanner system is provided. The method includes the steps of: providing a wafer having a plurality of shot areas, wherein each shot area has a plurality of alignment marks; determining a first outer zone of the wafer, wherein the first outer zone includes a first portion of the shot areas along a first outer edge of the wafer; determining a scan path according to the shot areas of the first outer zone; and performing an aligning process to each shot area of the first outer zone according to the scan path and an alignment mark of each shot area of the first outer zone.

Abstract translation: 提供了一种用于曝光扫描仪系统的边缘优势对准方法。 该方法包括以下步骤：提供具有多个拍摄区域的晶片，其中每个拍摄区域具有多个对准标记; 确定所述晶片的第一外部区域，其中所述第一外部区域沿所述晶片的第一外部边缘包括所述引射区域的第一部分; 根据所述第一外部区域的拍摄区域确定扫描路径; 以及根据所述扫描路径和所述第一外部区域的每个拍摄区域的对准标记，对所述第一外部区域的每个拍摄区域进行对准处理。

公开(公告)号：US20150170904A1

公开(公告)日：2015-06-18

申请号：US14585457

申请日：2014-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Di TSEN ,  Yi-Ping HSIEH ,  Chen-Yen HUANG ,  Shin-Rung LU ,  Jong-I MOU

IPC: H01L21/027 ,  H01L21/66

CPC classification number: G03F7/70633 ,  G03F9/7003 ,  G03F9/7019 ,  H01L21/0274 ,  H01L22/12 ,  H01L22/20

Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

Abstract translation: 提供了一种处理第一和第二半导体晶片的方法。 第一和第二半导体晶片中的每一个在第一层上具有第一层和第二层。 使用第一场间校正和第一场内校正在第一半导体晶片上的第一层上执行第一光刻处理。 确定第一光刻工艺的覆盖误差。 基于第一场间校正，第一场校正和测量的重叠误差来计算第二场校正和第二场校正。 基于第二场间校正和第二场内校正，在第二半导体晶片上的第二层上执行第二光刻处理。

公开(公告)号：US20140240706A1

公开(公告)日：2014-08-28

申请号：US14252612

申请日：2014-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Yao LEE ,  Ying-Ying WANG ,  Yi-Ping HSIEH ,  Heng-Hsin LIU

IPC: G01B11/14

CPC classification number: G03F7/70633 ,  G01B11/14 ,  G01B2210/56

Abstract: A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies.

Abstract translation: 测量晶片叠加计量的过程，晶片具有多个图案化层。 该过程开始于从数据库中检索历史叠加计量，并且测量第一组晶片的实际重叠计量。 另一方面，第二组晶片的虚拟覆盖计量学用所检索的历史过度计量来计算。 第一组晶圆的真实覆盖计量学和第二组晶圆的虚拟覆盖计量学作为历史重叠计量存储到数据库。