公开(公告)号：US10204843B2

公开(公告)日：2019-02-12

申请号：US15808184

申请日：2017-11-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Ruei Lin ,  Yen-Ming Peng ,  Han-Wei Yang ,  Chen-Chung Lai

IPC分类号： H01L23/528 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522

摘要： A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.

公开(公告)号：US09299621B2

公开(公告)日：2016-03-29

申请号：US14024688

申请日：2013-09-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Han-Wei Yang ,  Yi-Ruei Lin ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC分类号： H01L23/544 ,  H01L21/66 ,  H01L27/088

CPC分类号： H01L22/14 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

摘要翻译： 集成电路包括布置在硅衬底上的多个横向扩散测量结构。 横向扩散测量结构包括p型区域和n型区域，其协作地跨越横向扩散测量结构的相对外边缘之间的预定初始距离。 在发生掺杂剂扩散之后，p型和n型区域在预期位于目标连接位置处的p-n结处相交。

公开(公告)号：US09070687B2

公开(公告)日：2015-06-30

申请号：US13930161

申请日：2013-06-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC分类号： H01L23/52 ,  H01L23/525 ,  H01L21/306

CPC分类号： H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

摘要翻译： 提供具有金属保险丝的半导体器件。 金属熔断器连接电子部件（例如，晶体管）和接地的现有虚拟特征。 金属保险丝的保护可以设计为在金属化形成工艺开始时开始。 接地的虚拟特征提供了在线路过程的整个后端期间等离子体对地面充电的路径。 金属保险丝是与二极管相反的过程电平保护，这是电路级保护。 作为工艺级保护，金属保险丝保护随后形成的电路。 此外，除了已经实现的内部虚拟图案之外，芯片中的金属熔断器不需要额外的有源区域。

公开(公告)号：US10014251B2

公开(公告)日：2018-07-03

申请号：US15062063

申请日：2016-03-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC分类号： H01L23/525 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/167 ,  H01L21/56 ,  H01L23/31 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

公开(公告)号：US09472508B2

公开(公告)日：2016-10-18

申请号：US14987429

申请日：2016-01-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Ruei Lin ,  Yen-Ming Peng ,  Han-Wei Yang ,  Chen-Chung Lai

IPC分类号： H01L23/58 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532

CPC分类号： H01L23/3192 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76822 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.

摘要翻译： 提供半导体器件结构及其制造方法。 半导体结构包括衬底和形成在衬底上的互连结构。 互连结构包括形成在第一介电层中的第一介电层和第一应力减小结构。 互连结构还包括形成在第一介电层中的第一导电特征，并且第一导电特征被第一应力减小结构包围。

公开(公告)号：US09252047B2

公开(公告)日：2016-02-02

申请号：US14162158

申请日：2014-01-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Yi-Ruei Lin ,  Yen-Ming Peng ,  Han-Wei Yang ,  Chen-Chung Lai

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3192 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76822 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure.

摘要翻译： 提供半导体器件结构的实施例及其制造方法。 半导体器件结构包括衬底和形成在衬底上的第一层。 半导体器件结构还包括形成在第一层中的应力减小结构，并且第一层的一部分被应力减小结构包围。 半导体器件结构还包括形成在由应力减小结构包围的第一层的部分中的导电特征。

公开(公告)号：US09818666B2

公开(公告)日：2017-11-14

申请号：US15295043

申请日：2016-10-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Ruei Lin ,  Yen-Ming Peng ,  Han-Wei Yang ,  Chen-Chung Lai

IPC分类号： H01L23/528 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L23/3192 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76822 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.

公开(公告)号：US09299658B2

公开(公告)日：2016-03-29

申请号：US14717995

申请日：2015-05-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L23/525 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/167

CPC分类号： H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

摘要翻译： 提供了具有金属熔断器的半导体器件及其制造方法。 金属熔断器连接电子部件（例如，晶体管）和接地的现有虚拟特征。 金属保险丝的保护可以设计为在金属化形成工艺开始时开始。 接地的虚拟特征提供了在线路过程的整个后端期间等离子体对地面充电的路径。 金属保险丝是与二极管相反的过程电平保护，这是电路级保护。 作为工艺级保护，金属保险丝保护随后形成的电路。 此外，除了已经实现的内部虚拟图案之外，芯片中的金属熔断器不需要额外的有源区域。

公开(公告)号：US20150069395A1

公开(公告)日：2015-03-12

申请号：US14024688

申请日：2013-09-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Han-Wei Yang ,  Yi-Ruei Lin ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC分类号： H01L23/544 ,  H01L29/08 ,  H01L21/66

CPC分类号： H01L22/14 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

摘要翻译： 集成电路包括布置在硅衬底上的多个横向扩散测量结构。 横向扩散测量结构包括p型区域和n型区域，其协作地跨越横向扩散测量结构的相对外边缘之间的预定初始距离。 在发生掺杂剂扩散之后，p型和n型区域在预期位于目标连接位置处的p-n结处相交。

公开(公告)号：US20150001592A1

公开(公告)日：2015-01-01

申请号：US13930161

申请日：2013-06-28

申请人： Taiwan Semiconductor Manufacturing Co., LTD.

发明人： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC分类号： H01L23/525 ,  H01L21/306

CPC分类号： H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

摘要翻译： 提供具有金属保险丝的半导体器件。 金属熔断器连接电子部件（例如，晶体管）和接地的现有虚拟特征。 金属保险丝的保护可以设计为在金属化形成工艺开始时开始。 接地的虚拟特征提供了在线路过程的整个后端期间等离子体对地面充电的路径。 金属保险丝是与二极管相反的过程电平保护，这是电路级保护。 作为工艺级保护，金属保险丝保护随后形成的电路。 此外，除了已经实现的内部虚拟图案之外，芯片中的金属熔断器不需要额外的有源区域。