公开(公告)号：US10204843B2

公开(公告)日：2019-02-12

申请号：US15808184

申请日：2017-11-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Ruei Lin ,  Yen-Ming Peng ,  Han-Wei Yang ,  Chen-Chung Lai

IPC分类号： H01L23/528 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522

摘要： A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.

公开(公告)号：US10157810B2

公开(公告)日：2018-12-18

申请号：US15714099

申请日：2017-09-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC分类号： H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/40 ,  H01L29/41 ,  H01L23/29 ,  H01L23/532

摘要： Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US10014251B2

公开(公告)日：2018-07-03

申请号：US15062063

申请日：2016-03-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC分类号： H01L23/525 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/167 ,  H01L21/56 ,  H01L23/31 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

公开(公告)号：US09472508B2

公开(公告)日：2016-10-18

申请号：US14987429

申请日：2016-01-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Ruei Lin ,  Yen-Ming Peng ,  Han-Wei Yang ,  Chen-Chung Lai

IPC分类号： H01L23/58 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532

CPC分类号： H01L23/3192 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76822 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.

摘要翻译： 提供半导体器件结构及其制造方法。 半导体结构包括衬底和形成在衬底上的互连结构。 互连结构包括形成在第一介电层中的第一介电层和第一应力减小结构。 互连结构还包括形成在第一介电层中的第一导电特征，并且第一导电特征被第一应力减小结构包围。

公开(公告)号：US09252047B2

公开(公告)日：2016-02-02

申请号：US14162158

申请日：2014-01-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Yi-Ruei Lin ,  Yen-Ming Peng ,  Han-Wei Yang ,  Chen-Chung Lai

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3192 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76822 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure.

摘要翻译： 提供半导体器件结构的实施例及其制造方法。 半导体器件结构包括衬底和形成在衬底上的第一层。 半导体器件结构还包括形成在第一层中的应力减小结构，并且第一层的一部分被应力减小结构包围。 半导体器件结构还包括形成在由应力减小结构包围的第一层的部分中的导电特征。

公开(公告)号：US09093373B2

公开(公告)日：2015-07-28

申请号：US13965294

申请日：2013-08-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-Chia Chang ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L27/146 ,  H01L29/78 ,  H01L21/762

CPC分类号： H01L21/265 ,  H01L21/26513 ,  H01L21/76286 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1463 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction. A diffusion barrier structure, which is beneath the surface of the semiconductor substrate and extends along a side of the p-n junction, limits lateral diffusion between the p-type region and n-type region.

摘要翻译： 集成电路包括形成在半导体衬底的表面下方的p型区域和形成在半导体衬底的表面下方的n型区域。 n型区域在p-n结处与p型区域相遇。 在半导体衬底的表面下方并且沿着p-n结的一侧延伸的扩散阻挡结构限制了p型区域和n型区域之间的横向扩散。

公开(公告)号：US20200111719A1

公开(公告)日：2020-04-09

申请号：US16705469

申请日：2019-12-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC分类号： H01L23/31 ,  H01L21/768 ,  H01L23/29 ,  H01L23/48 ,  H01L23/482 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L29/40 ,  H01L29/41

摘要： Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US20190115273A1

公开(公告)日：2019-04-18

申请号：US16218842

申请日：2018-12-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC分类号： H01L23/31 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L23/29 ,  H01L29/41 ,  H01L29/40 ,  H01L23/522 ,  H01L23/482

CPC分类号： H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US20160247741A1

公开(公告)日：2016-08-25

申请号：US15146012

申请日：2016-05-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC分类号： H01L23/31 ,  H01L23/532 ,  H01L23/29 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an opening extending through the layer. A plurality of bar or pillar structures or a tapered region are arranged in a peripheral portion of the opening and laterally surround a central portion of the opening. A metal body extends through the central portion of the opening.

摘要翻译： 在一些实施例中公开了一种半导体器件。 该器件包括衬底和设置在衬底上的层。 该层包括延伸穿过该层的开口。 多个杆或柱结构或锥形区域布置在开口的周边部分中并横向围绕开口的中心部分。 金属体延伸穿过开口的中心部分。

公开(公告)号：US09076804B2

公开(公告)日：2015-07-07

申请号：US13974400

申请日：2013-08-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC分类号： H01L23/485 ,  H01L21/4763 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L23/528 ,  H01L29/40

CPC分类号： H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.

摘要翻译： 公开了一种具有增强的钝化完整性的半导体器件。 该器件包括衬底，第一层和金属层。 第一层形成在衬底上。 第一层包括通孔开口和靠近通孔开口的锥形部分。 金属层形成在通孔开口和第一层的锥形部分之上。 金属层基本上没有间隙和空隙。