公开(公告)号：US20240379740A1

公开(公告)日：2024-11-14

申请号：US18781290

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US11694924B2

公开(公告)日：2023-07-04

申请号：US17365911

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L23/485 ,  H01L21/8238 ,  H01L29/165 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/76814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.

公开(公告)号：US20210384294A1

公开(公告)日：2021-12-09

申请号：US17445692

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US10367059B2

公开(公告)日：2019-07-30

申请号：US15700115

申请日：2017-09-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cong-Min Fang ,  Kang-Min Kuo ,  Shi-Min Wu

IPC: H01L29/06 ,  H01L21/762

Abstract: A method of manufacturing a semiconductor structure includes the following steps. A first raised portion is formed on a semiconductor substrate. The height of the first raised portion is reduced, and a dielectric material is formed over the first raised portion. The dielectric material is annealed such that the first raised portion is tilted.

公开(公告)号：US10325914B2

公开(公告)日：2019-06-18

申请号：US16057838

申请日：2018-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Chi Tsai ,  Kang-Min Kuo

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/265

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. An effective lattice constant of the dielectric layer doped with the strain modulator is different from an original lattice constant of the dielectric layer prior to be doped with the strain modulator, wherein the strain modulator at least comprises silicon.

公开(公告)号：US10147805B2

公开(公告)日：2018-12-04

申请号：US14815349

申请日：2015-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Lung Chen ,  Kang-Min Kuo ,  Wen-Hsin Chan

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.

公开(公告)号：US09960246B2

公开(公告)日：2018-05-01

申请号：US15369460

申请日：2016-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Lian ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Chih-Wei Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/517 ,  H01L21/28158 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.

公开(公告)号：US09515158B1

公开(公告)日：2016-12-06

申请号：US14918054

申请日：2015-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Lian ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Chih-Wei Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/517 ,  H01L21/28158 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. In addition, the insertion layer is made of M1Ox, and M1 is a metal, O is oxygen, and x is a value greater than 4.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括衬底，在衬底上形成的界面层，以及形成在界面层上的插入层。 半导体结构还包括形成在插入层上的栅极电介质层和形成在栅极介电层上的栅极结构。 此外，插入层由M1Ox制成，M1为金属，O为氧，x为大于4的值。

公开(公告)号：US11728376B2

公开(公告)日：2023-08-15

申请号：US17445692

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US11081571B2

公开(公告)日：2021-08-03

申请号：US16928942

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung Chen ,  Kang-Min Kuo ,  Wen-Hsin Chan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation.