公开(公告)号：US09184087B2

公开(公告)日：2015-11-10

申请号：US14142527

申请日：2013-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tsung-Yu Chiang ,  Chung-Wei Lin ,  Kuang-Hsin Chen ,  Bor-Zen Tien

IPC: H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L21/266 ,  H01L21/263

CPC classification number: H01L21/76237 ,  H01L21/2636 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and protruding through a top surface thereof. The semiconductor device also includes a second fin partially surrounded by a second isolation structure and protruding through a top surface thereof. The top surface of the first isolation structure is higher than the top surface of the second isolation structure such that the second fin has a height higher than that of the first fin. The second isolation structure has a dopant concentration higher than that of the first isolation structure.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括由第一隔离结构部分地被其顶表面突出的第一鳍片。 半导体器件还包括被第二隔离结构部分地包围并突出通过其顶表面的第二鳍。 第一隔离结构的顶表面高于第二隔离结构的顶表面，使得第二翅片的高度高于第一隔离结构的高度。 第二隔离结构的掺杂浓度高于第一隔离结构。

公开(公告)号：US09122828B2

公开(公告)日：2015-09-01

申请号：US13896373

申请日：2013-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Yu Chiang ,  Kuang-Hsin Chen ,  Song-Bor Lee ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells.

Abstract translation: 设计用于多个不同逻辑操作（LOP）单元技术的布局的系统和方法包括为多个不同的LOP技术中的每个LOP单元技术定义优先级，并且形成用于形成的多个不同LOP单元的布局 具有较高优先级LOP技术的至少一些LOP单元的衬底与较低优先级的LOP技术的LOP单元重叠。 该系统可以包括耦合到存储器的处理器，其中存储的代码为多个LOP单元中的每个不同的单元技术定义优先级，并且（当代码被执行时）处理器形成多个不同的LOP单元的布局。 较高优先级的LOP技术的所有LOP单元重叠优先级较低的LOP单元。 该系统或方法还避免了较低优先级的LOP单元与较高优先级的LOP单元的重叠。

公开(公告)号：US20140344770A1

公开(公告)日：2014-11-20

申请号：US13896373

申请日：2013-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Yu CHIANG ,  Kuang-Hsin Chen ,  Song-Bor Lee ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells.

Abstract translation: 设计用于多个不同逻辑操作（LOP）单元技术的布局的系统和方法包括为多个不同的LOP技术中的每个LOP单元技术定义优先级，并且形成用于形成的多个不同LOP单元的布局 具有较高优先级LOP技术的至少一些LOP单元的衬底与较低优先级的LOP技术的LOP单元重叠。 该系统可以包括耦合到存储器的处理器，其中存储的代码为多个LOP单元中的每个不同的单元技术定义优先级，并且（当代码被执行时）处理器形成多个不同的LOP单元的布局。 较高优先级的LOP技术的所有LOP单元重叠优先级较低的LOP单元。 该系统或方法还避免了较低优先级的LOP单元与较高优先级的LOP单元的重叠。

公开(公告)号：US10157810B2

公开(公告)日：2018-12-18

申请号：US15714099

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/40 ,  H01L29/41 ,  H01L23/29 ,  H01L23/532

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US10014251B2

公开(公告)日：2018-07-03

申请号：US15062063

申请日：2016-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC: H01L23/525 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/167 ,  H01L21/56 ,  H01L23/31 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

公开(公告)号：US09412866B2

公开(公告)日：2016-08-09

申请号：US13924731

申请日：2013-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gwo-Chyuan Kuoh ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien ,  Yen-Ming Peng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L29/7843 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/823871 ,  H01L23/00 ,  H01L29/7842 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.

Abstract translation: 本公开内容涉及具有一个或多个后端行（BEOL）选择应力膜的集成芯片，其应用提高BEOL选择应力膜的半导体器件的性能的应力，以及相关的方法 形成。 在一些实施例中，集成芯片具有带有一个或多个具有第一器件类型的半导体器件的半导体衬底。 应力传递元件位于一个或多个半导体器件上方的位置处的后端行堆叠中。 选择应力膜位于应力转移元件上方。 选择应力膜在应力转移元件上引起应力，其中应力具有取决于一个或多个半导体器件的第一器件类型的压缩或拉伸状态。 应力作用在一个或多个半导体器件上以提高它们的性能。

公开(公告)号：US09093528B2

公开(公告)日：2015-07-28

申请号：US13905438

申请日：2013-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ming Peng ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/498 ,  H01L21/8234

CPC classification number: H01L29/7843 ,  H01L21/82345 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.

Abstract translation: 本公开涉及具有一个或多个后端（BEOL）应力补偿层的集成芯片，其减小一个或多个下层半导体器件上的应力，以及相关联的形成方法。 在一些实施例中，集成芯片具有带有一个或多个半导体器件的半导体衬底。 应力元件位于覆盖一个或多个半导体器件的位置处的后端行堆叠中。 应力层位于应力元件上方会对应力元件产生应力。 位于应力元件上方的应力补偿层提供反应力，以减轻应力层对受应力元件的应力。 通过减少在应力元件上产生的应力，减小半导体衬底上的应力，提高一个或多个半导体器件的性能的均匀性。

公开(公告)号：US09093373B2

公开(公告)日：2015-07-28

申请号：US13965294

申请日：2013-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chia Chang ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L27/146 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/76286 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1463 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction. A diffusion barrier structure, which is beneath the surface of the semiconductor substrate and extends along a side of the p-n junction, limits lateral diffusion between the p-type region and n-type region.

Abstract translation: 集成电路包括形成在半导体衬底的表面下方的p型区域和形成在半导体衬底的表面下方的n型区域。 n型区域在p-n结处与p型区域相遇。 在半导体衬底的表面下方并且沿着p-n结的一侧延伸的扩散阻挡结构限制了p型区域和n型区域之间的横向扩散。

公开(公告)号：US11101360B2

公开(公告)日：2021-08-24

申请号：US16590220

申请日：2019-10-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Wen-Hsing Hsieh ,  Wen-Yuan Chen ,  Jon-Hsu Ho ,  Song-Bor Lee ,  Bor-Zen Tien

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L29/08 ,  H01L29/786 ,  H01L29/24

Abstract: A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.

公开(公告)号：US11069791B2

公开(公告)日：2021-07-20

申请号：US16601721

申请日：2019-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Yi-Ju Hsu ,  Jon-Hsu Ho ,  Song-Bor Lee ,  Bor-Zen Tien

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.