公开(公告)号：US11551966B2

公开(公告)日：2023-01-10

申请号：US17000122

申请日：2020-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Shan Chen ,  Chan-Syun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528 ,  H01L21/32 ,  H01L21/02

Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

公开(公告)号：US10157773B1

公开(公告)日：2018-12-18

申请号：US15823687

申请日：2017-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Shan Chen ,  Chan-Syun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528 ,  H01L21/32 ,  H01L21/02

Abstract: A method of forming a semiconductor structure is provided. In this method, a semiconductor substrate is provided. A SoC layer is formed on the semiconductor substrate. A hard mask layer is formed over the SoC layer. The hard mask layer is patterned to expose a portion of the SoC layer. At least one opening is formed on the portion of the SoC layer using an ALE operation, thereby enabling the remaining portion of the SoC layer adjacent to the at least one opening to have a re-entrant angle included between a sidewall of the SoC layer and a bottom of the SoC layer.

公开(公告)号：US11978640B2

公开(公告)日：2024-05-07

申请号：US17226332

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Yi-Shan Chen ,  Chih-Kai Yang ,  Pinyen Lin

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/66

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L22/12

Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.

公开(公告)号：US20230155005A1

公开(公告)日：2023-05-18

申请号：US17663278

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Hao-Heng Liu ,  Po-Chin Chang ,  Yi-Shan Chen ,  Ming-Huan Tsai

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/7851 ,  H01L21/823481 ,  H01L21/823418 ,  H01L29/41791 ,  H01L27/0886

Abstract: A method includes forming a first fin and a second fin protruding from a substrate; forming an isolation layer surrounding the first fin and the second fin; epitaxially growing a first epitaxial region on the first fin and a second epitaxial region on the second fin, wherein the first epitaxial region and the second epitaxial region are merged together; performing an etching process on the first epitaxial region and the second epitaxial region, wherein the etching process separates the first epitaxial region from the second epitaxial region; depositing a dielectric material between the first epitaxial region and the second epitaxial region; and forming a first gate stack extending over the first fin.

公开(公告)号：US10755968B2

公开(公告)日：2020-08-25

申请号：US16222787

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Shan Chen ,  Chan-Syun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528 ,  H01L21/32 ,  H01L21/02

Abstract: A method is provided. A sacrificial layer is formed over a semiconductor substrate. An etching process is performed to form an opening in the sacrificial layer. The etching process includes a first cycle and a second cycle performed after the first cycle, and each of the first cycle and the second cycle includes applying a passivation gas and an etchant gas over the sacrificial layer, and performing an ionized gas bombardment on the sacrificial layer after applying the passivation gas and the etchant gas over the sacrificial layer. The passivation gas is applied at a first flow rate in the first cycle and is applied at a second flow rate in the second cycle, and the first flow rate is higher than the second flow rate.