公开(公告)号：US09553191B1

公开(公告)日：2017-01-24

申请号：US14942980

申请日：2015-11-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-I Liao ,  Mon-Nan How ,  Shih-Chieh Chang ,  Ying-Min Chou ,  Ting-Chang Chang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/283 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a FinFET includes at last the following steps. A semiconductor substrate is patterned to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin between the trenches. Insulators are formed in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. A strained material doped with a conductive dopant is formed over portions of the semiconductor fin revealed by the gate stack, and the strained material is formed by selectively growing a bulk layer with a gradient doping concentration.

摘要翻译： 制造FinFET的方法最后包括以下步骤。 图案化半导体衬底以在半导体衬底中形成多个沟槽，并在沟槽之间形成至少一个半导体鳍片。 绝缘子形成在沟槽中。 栅极叠层形成在半导体鳍片的部分和绝缘体的上部。 掺杂有导电掺杂剂的应变材料形成在半导体鳍片的由栅极叠层显露的部分上，并且应变材料通过选择性地生长具有梯度掺杂浓度的体层而形成。

公开(公告)号：US10134896B2

公开(公告)日：2018-11-20

申请号：US13782112

申请日：2013-03-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun Hsiung Tsai ,  Sheng-Wen Yu ,  Ying-Min Chou ,  Yi-Fang Pai

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/66

摘要： A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.

公开(公告)号：US09698263B2

公开(公告)日：2017-07-04

申请号：US14945542

申请日：2015-11-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Lai-Wan Chong ,  Wen-Chu Hsiao ,  Ying-Min Chou ,  Hsiang-Hsiang Ko

IPC分类号： H01L29/04 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

摘要： A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.