公开(公告)号：US20210296571A1

公开(公告)日：2021-09-23

申请号：US17339785

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Yu-Jen Chien ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Yao-Shien Huang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.

公开(公告)号：US20230389438A1

公开(公告)日：2023-11-30

申请号：US18447383

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Wu Meng Yu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Han-Ting Tsai ,  Yu-Jen Chien

IPC: H10N50/01 ,  H01F10/32 ,  H10B61/00 ,  G11C11/16 ,  H01F41/34 ,  H10N50/80

CPC classification number: H10N50/01 ,  H01F10/3254 ,  H10B61/00 ,  G11C11/161 ,  H01F41/34 ,  H10N50/80

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

公开(公告)号：US11749524B2

公开(公告)日：2023-09-05

申请号：US17339785

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Yu-Jen Chien ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Yao-Shien Huang

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/04 ,  H10B61/00 ,  H10N50/01

CPC classification number: H01L21/0234 ,  H01L21/044 ,  H01L21/28088 ,  H10B61/00 ,  H10N50/01

Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.

公开(公告)号：US11864467B2

公开(公告)日：2024-01-02

申请号：US17461132

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Wu Meng Yu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Han-Ting Tsai ,  Yu-Jen Chien

IPC: H10N50/01 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H10B61/00 ,  H10N50/80

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

公开(公告)号：US20210391534A1

公开(公告)日：2021-12-16

申请号：US17461132

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Wu Meng Yu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Han-Ting Tsai ,  Yu-Jen Chien

IPC: H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

公开(公告)号：US11985904B2

公开(公告)日：2024-05-14

申请号：US17168974

申请日：2021-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Jen Chien ,  Jung-Tang Wu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Meng-Yu Wu

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

公开(公告)号：US20230369044A1

公开(公告)日：2023-11-16

申请号：US18360259

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Yu-Jen Chien ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Yao-Shien Huang

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/04 ,  H10B61/00 ,  H10N50/01

CPC classification number: H01L21/0234 ,  H01L21/28088 ,  H01L21/044 ,  H10B61/00 ,  H10N50/01

Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.