-
公开(公告)号：US12274181B2
公开(公告)日：2025-04-08
申请号：US18302538
申请日：2023-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Feng Yin , An-Shen Chang , Han-Ting Tsai , Qiang Fu
Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.
-
公开(公告)号：US12154608B2
公开(公告)日：2024-11-26
申请号：US18366779
申请日：2023-08-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Bo-Jhih Shen , Kuang-I Liu , Joung-Wei Liou , Jinn-Kwei Liang , Yi-Wei Chiu , Chin-Hsing Lin , Li-Te Hsu , Han-Ting Tsai , Cheng-Yi Wu , Shih-Ho Lin
Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.
-
公开(公告)号：US20230255120A1
公开(公告)日：2023-08-10
申请号：US18302538
申请日：2023-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Feng Yin , An-Shen Chang , Han-Ting Tsai , Qiang Fu
CPC classification number: H10N50/80 , G11C11/161 , G11C11/1655 , G11C11/1657 , H10B61/22 , H10N50/01
Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.
-
公开(公告)号：US20200006423A1
公开(公告)日：2020-01-02
申请号：US16270484
申请日：2019-02-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Te Lin , Yen-Chung Ho , Pin-Cheng Hsu , Han-Ting Tsai , Katherine Chiang
Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.
-
公开(公告)号：US10276794B1
公开(公告)日：2019-04-30
申请号：US15799416
申请日：2017-10-31
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tai-Yen Peng , Hui-Hsien Wei , Wei-Chih Wen , Pin-Ren Dai , Chien-Min Lee , Han-Ting Tsai , Jyu-Horng Shieh , Chung-Te Lin
Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.
-
Patent Agency Ranking
公开(公告)号：US09496264B2
公开(公告)日：2016-11-15
申请号：US14621814
申请日：2015-02-13
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
Inventor： Kai-Hsuan Lee , Cheng-Yu Yang , Hsiang-Ku Shen , Han-Ting Tsai , Yimin Huang
IPC: H01L27/12 , H01L27/092 , H01L29/78 , H01L21/335 , H01L29/207 , H01L29/36 , H01L29/66 , H01L21/8234 , H01L21/266 , H01L29/161 , H01L29/49
CPC classification number: H01L29/7848 , H01L21/823814 , H01L21/823871 , H01L27/092 , H01L29/161 , H01L29/267 , H01L29/495 , H01L29/66545 , H01L29/66636 , H01L29/66795
Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate. The semiconductor device structure also includes a first doped structure over the semiconductor substrate and adjacent to the first gate stack. The first doped structure includes a III-V compound semiconductor material and a dopant. The semiconductor device structure further includes a second doped structure over the semiconductor substrate and adjacent to the second gate stack. The second doped structure includes the III-V compound semiconductor material and the dopant. One of the first doped structure and the second doped structure is an n-type semiconductor structure, and the other one of the first doped structure and the second doped structure is a p-type semiconductor structure.
Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底和半导体衬底上的第一栅极堆叠和第二栅极堆叠。 半导体器件结构还包括在半导体衬底上并与第一栅极叠层相邻的第一掺杂结构。 第一掺杂结构包括III-V族化合物半导体材料和掺杂剂。 半导体器件结构还包括在半导体衬底上并与第二栅极堆叠相邻的第二掺杂结构。 第二掺杂结构包括III-V族化合物半导体材料和掺杂剂。 第一掺杂结构和第二掺杂结构之一是n型半导体结构，第一掺杂结构和第二掺杂结构中的另一个是p型半导体结构。
-
公开(公告)号：US11968843B2
公开(公告)日：2024-04-23
申请号：US16270484
申请日：2019-02-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Te Lin , Yen-Chung Ho , Pin-Cheng Hsu , Han-Ting Tsai , Katherine Chiang
CPC classification number: H10B61/20 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/161 , G11C11/1653 , G11C11/1673 , G11C11/1675 , H10N50/01 , H10N50/80
Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.
-
公开(公告)号：US20230389438A1
公开(公告)日：2023-11-30
申请号：US18447383
申请日：2023-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jung-Tang Wu , Wu Meng Yu , Szu-Hua Wu , Chin-Szu Lee , Han-Ting Tsai , Yu-Jen Chien
CPC classification number: H10N50/01 , H01F10/3254 , H10B61/00 , G11C11/161 , H01F41/34 , H10N50/80
Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
-
9.发明申请公开(公告)号：US20210111175A1
公开(公告)日：2021-04-15
申请号：US17129763
申请日：2020-12-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wei-Chih Wen , Han-Ting Tsai , Chung-Te Lin
IPC: H01L27/06 , H01L21/822 , H01L21/768 , H01L27/22 , H01L23/525 , H01L23/522 , H01L27/24 , H01L45/00 , H01L43/12
Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.
-
公开(公告)号：US10700125B2
公开(公告)日：2020-06-30
申请号：US16416529
申请日：2019-05-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Katherine H. Chiang , Chung-Te Lin , Min Cao , Han-Ting Tsai , Pin-Cheng Hsu , Yen-Chung Ho
Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.
-
-
-
-
-
-
-
-
-
Search Results
36
records
(took 0.022 seconds)
