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公开(公告)号:US20240266303A1
公开(公告)日:2024-08-08
申请号:US18635315
申请日:2024-04-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shang-Yun Hou , Weiming Chris Chen , Kuo-Chiang Ting , Hsien-Pin Hu , Wen-Chih Chiou , Chen-Hua Yu
IPC: H01L23/00 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/538 , H01L25/00 , H01L25/065
CPC classification number: H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/5383 , H01L23/5385 , H01L23/5386 , H01L24/16 , H01L25/0655 , H01L25/50 , H01L2221/6835 , H01L2224/16227 , H01L2924/3511 , H01L2924/35121
Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.
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公开(公告)号:US12027455B2
公开(公告)日:2024-07-02
申请号:US17852961
申请日:2022-06-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Weiming Chris Chen , Kuo-Chiang Ting , Shang-Yun Hou
IPC: H01L23/498 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/538
CPC classification number: H01L23/49861 , H01L21/486 , H01L21/56 , H01L23/3121 , H01L23/5384
Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.
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公开(公告)号:US20220262742A1
公开(公告)日:2022-08-18
申请号:US17339745
申请日:2021-06-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shang-Yun Hou , Weiming Chris Chen , Kuo-Chiang Ting , Hsien-Pin Hu , Wen-Chih Chiou , Chen-Hua Yu
IPC: H01L23/00 , H01L25/065 , H01L23/31 , H01L23/538 , H01L21/683 , H01L21/48 , H01L21/56 , H01L25/00
Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.
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公开(公告)号:US11380611B2
公开(公告)日:2022-07-05
申请号:US16919298
申请日:2020-07-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Weiming Chris Chen , Kuo-Chiang Ting , Shang-Yun Hou
IPC: H01L23/498 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/538
Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.
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公开(公告)号:US20210082894A1
公开(公告)日:2021-03-18
申请号:US16572619
申请日:2019-09-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Weiming Chris Chen , Chi-Hsi Wu , Chih-Wei Wu , Kuo-Chiang Ting , Szu-Wei Lu , Shang-Yun Hou , Ying-Ching Shih , Hsien-Ju Tsou , Cheng-Chieh Li
Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.
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公开(公告)号:US11996371B2
公开(公告)日:2024-05-28
申请号:US17339745
申请日:2021-06-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shang-Yun Hou , Weiming Chris Chen , Kuo-Chiang Ting , Hsien-Pin Hu , Wen-Chih Chiou , Chen-Hua Yu
IPC: H01L21/56 , H01L21/48 , H01L21/683 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/00 , H01L25/065
CPC classification number: H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/5383 , H01L23/5385 , H01L23/5386 , H01L24/16 , H01L25/0655 , H01L25/50 , H01L2221/6835 , H01L2224/16227 , H01L2924/3511 , H01L2924/35121
Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.
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公开(公告)号:US20220359433A1
公开(公告)日:2022-11-10
申请号:US17869296
申请日:2022-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wen Hsin Wei , Hsien-Pin Hu , Shang-Yun Hou , Weiming Chris Chen
IPC: H01L23/00 , H01L21/768 , H01L23/58
Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.
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公开(公告)号:US20220359231A1
公开(公告)日:2022-11-10
申请号:US17815434
申请日:2022-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih Ting Lin , Szu-Wei Lu , Kuo-Chiang Ting , Shang-Yun Hou , Chi-Hsi Wu , Weiming Chris Chen
IPC: H01L21/56 , H01L21/768 , H01L21/48 , H01L23/538
Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.
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公开(公告)号:US20250054879A1
公开(公告)日:2025-02-13
申请号:US18931965
申请日:2024-10-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wen Hsin Wei , Hsien-Pin Hu , Shang-Yun Hou , Weiming Chris Chen
IPC: H01L23/00 , H01L21/768 , H01L23/31 , H01L23/532 , H01L23/58 , H01L25/00 , H01L25/065
Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.
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公开(公告)号:US20240387198A1
公开(公告)日:2024-11-21
申请号:US18786739
申请日:2024-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih Ting Lin , Szu-Wei Lu , Kuo-Chiang Ting , Shang-Yun Hou , Chi-Hsi Wu , Weiming Chris Chen
IPC: H01L21/56 , H01L21/48 , H01L21/768 , H01L23/31 , H01L23/538
Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.
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