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    Method and Structure for Gap Filling Improvement
    6.
    发明申请
    Method and Structure for Gap Filling Improvement 审中-公开

    公开(公告)号：US20180040617A1

    公开(公告)日：2018-02-08

    申请号：US15783448

    申请日：2017-10-13

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ying-Hao Su ,  Yu-Chung Su ,  Yu-Lun Liu ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Kuei-Shun Chen

    IPC: H01L27/088 ,  H01L21/027 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8234

    Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

    Method and Structure for Mandrel and Spacer Patterning
    7.
    发明申请
    Method and Structure for Mandrel and Spacer Patterning 有权
    心轴和间隔图案的方法和结构

    公开(公告)号：US20170017745A1

    公开(公告)日：2017-01-19

    申请号：US14801383

    申请日：2015-07-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chung-Ming Wang ,  Chih-Hsiung Peng ,  Chi-Kang Chang ,  Kuei-Shun Chen ,  Shih-Chi Fu

    IPC: G06F17/50 ,  H01L29/06 ,  H01L27/088

    CPC classification number: G06F17/5068 ,  G06F2217/02 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0653

    Abstract: A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.

    Abstract translation: 一种方法包括接收包括由第一空间分隔的第一和第二布局块的集成电路设计布局。 第一和第二布局块分别包括沿第一方向纵向定向的第一和第二线图案。 该方法还包括将虚拟图案添加到连接第一和第二线图案的第一空间。 该方法还包括以计算机可读格式输出心轴图案布局和切割图案布局。 心轴图案布局包括第一和第二线图案和虚设图案。 切割图案布局包括对应于第一空间的图案。 在实施例中，该方法还包括制造具有心轴图案布局的第一掩模并且制造具有切割图案布局的第二掩模。 在实施例中，该方法还包括用第一掩模和第二掩模图案化衬底。

    Enhanced FinFET process overlay mark
    8.
    发明授权
    Enhanced FinFET process overlay mark 有权
    增强型FinFET工艺叠加标记

    公开(公告)号：US09129974B2

    公开(公告)日：2015-09-08

    申请号：US14472018

    申请日：2014-08-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

    IPC: H01L23/544 ,  G03F7/20 ,  H01L27/088

    CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L27/0883 ,  H01L27/0886 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

    Abstract translation: 公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。 示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。 在基板上形成一个或多个电介质层和硬掩模。 图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。 间隔物形成在图案化的硬掩模层上。 垫片进一步限定重叠标记鳍片和有源器件鳍片。 覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。 蚀刻电介质层和衬底以进一步限定覆盖标记鳍。

    Enhanced FinFET Process Overlay Mark
    9.
    发明申请
    Enhanced FinFET Process Overlay Mark 有权
    增强型FinFET工艺叠加标记

    公开(公告)号：US20140367869A1

    公开(公告)日：2014-12-18

    申请号：US14472018

    申请日：2014-08-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

    IPC: H01L23/544 ,  G03F7/20 ,  H01L27/088

    CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L27/0883 ,  H01L27/0886 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

    Abstract translation: 公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。 示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。 在基板上形成一个或多个电介质层和硬掩模。 图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。 间隔物形成在图案化的硬掩模层上。 垫片进一步限定重叠标记鳍片和有源器件鳍片。 覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。 蚀刻电介质层和衬底以进一步限定覆盖标记鳍。

    Method of manufacturing a semiconductor device and semiconductor device
    10.
    发明授权
    Method of manufacturing a semiconductor device and semiconductor device 有权

    公开(公告)号：US12154975B2

    公开(公告)日：2024-11-26

    申请号：US17403867

    申请日：2021-08-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chi-Wen Hsieh ,  Chien-Ping Hung ,  Chi-Kang Chang ,  Shih-Chi Fu ,  Kuei-Shun Chen

    IPC: H01L27/118 ,  H01L29/66 ,  H01L29/78

    Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

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