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    Method and structure for gap filling improvement
    1.
    发明授权
    Method and structure for gap filling improvement 有权

    公开(公告)号：US10515953B2

    公开(公告)日：2019-12-24

    申请号：US15783448

    申请日：2017-10-13

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ying-Hao Su ,  Yu-Chung Su ,  Yu-Lun Liu ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Kuei-Shun Chen

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/027 ,  H01L29/66 ,  H01L21/768

    Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

    Method and Structure for Gap Filling Improvement
    2.
    发明申请
    Method and Structure for Gap Filling Improvement 审中-公开

    公开(公告)号：US20180040617A1

    公开(公告)日：2018-02-08

    申请号：US15783448

    申请日：2017-10-13

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ying-Hao Su ,  Yu-Chung Su ,  Yu-Lun Liu ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Kuei-Shun Chen

    IPC: H01L27/088 ,  H01L21/027 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8234

    Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

    METHOD FOR REMOVING A PATTERNED HARD MASK LAYER
    5.
    发明申请
    METHOD FOR REMOVING A PATTERNED HARD MASK LAYER 审中-公开
    用于去除图案硬掩模层的方法

    公开(公告)号：US20140120729A1

    公开(公告)日：2014-05-01

    申请号：US13666268

    申请日：2012-11-01

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yu-Lun Liu ,  Ying-Hao Su ,  Chia-Chu Liu ,  Kuei-Shun Chen

    IPC: H01L21/308 ,  G06F17/50

    CPC classification number: G06F17/50 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139

    Abstract: The present disclosure provides embodiments of a method that includes providing a substrate having a patterned material layer and a patterned hard mask layer disposed on the patterned material layer, wherein the patterned material layer includes a material feature having a first dimension and the patterned hard mask layer includes a hard mask feature covering the material feature. The method also includes forming, on the substrate and the hard mask feature, a patterned resist layer with an opening that exposes the hard mask feature and has a second dimension as a function of the first dimension; etching back the resist film; and removing the patterned hard mask layer.

    Abstract translation: 本公开提供了一种方法的实施例，其包括提供具有图案化材料层和设置在图案化材料层上的图案化硬掩模层的衬底，其中图案化材料层包括具有第一尺寸的材料特征和图案化硬掩模层 包括覆盖材料特征的硬掩模特征。 该方法还包括在衬底和硬掩模特征上形成具有暴露硬掩模特征并具有作为第一尺寸的函数的第二尺寸的开口的图案化抗蚀剂层; 蚀刻抗蚀剂膜; 并去除图案化的硬掩模层。

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