公开(公告)号：US20230032528A1

公开(公告)日：2023-02-02

申请号：US17389354

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Huang ,  Gao-Ming Wu ,  Yun-Feng Kao ,  Ming-Yen Chuang ,  Katherine H. Chiang

IPC: H01L29/08 ,  H01L29/10 ,  H01L21/8234

Abstract: Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.

公开(公告)号：US12148691B2

公开(公告)日：2024-11-19

申请号：US17704026

申请日：2022-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yun-Feng Kao ,  Chien-Hao Huang ,  Gao-Ming Wu ,  Katherine H Chiang

IPC: H01L23/522 ,  H01L49/02 ,  H10B12/00

Abstract: A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

公开(公告)号：US11848332B2

公开(公告)日：2023-12-19

申请号：US17383444

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Gao-Ming Wu ,  Katherine H. Chiang ,  Chien-Hao Huang ,  Chung-Te Lin

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/02565 ,  H01L27/127 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

公开(公告)号：US11695039B2

公开(公告)日：2023-07-04

申请号：US17389354

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Huang ,  Gao-Ming Wu ,  Yun-Feng Kao ,  Ming-Yen Chuang ,  Katherine H. Chiang

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/1033 ,  H01L29/66765

Abstract: Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.

公开(公告)号：US20230141313A1

公开(公告)日：2023-05-11

申请号：US17577037

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Huang ,  Gao-Ming Wu ,  Katherine H CHIANG ,  Chung-Te Lin

IPC: H01L29/417 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/41775 ,  H01L29/42364 ,  H01L29/4011

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.

公开(公告)号：US20230028561A1

公开(公告)日：2023-01-26

申请号：US17383444

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Gao-Ming Wu ,  Katherine H. CHIANG ,  Chien-Hao Huang ,  Chung-Te Lin

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

公开(公告)号：US20240079497A1

公开(公告)日：2024-03-07

申请号：US17901843

申请日：2022-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Huang ,  Gao-Ming Wu ,  Katherine H CHIANG ,  Chung-Te Lin

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/0847 ,  H01L29/66742 ,  H01L29/78696

Abstract: Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

公开(公告)号：US20230369107A1

公开(公告)日：2023-11-16

申请号：US18357251

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Shyue Lai ,  Gao-Ming Wu ,  Katherine H. Chiang ,  Chung-Te Lin

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L23/5226 ,  H01L21/76877 ,  H01L21/76832

Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.

公开(公告)号：US20230307351A1

公开(公告)日：2023-09-28

申请号：US17704026

申请日：2022-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yun-Feng Kao ,  Chien-Hao Huang ,  Gao-Ming Wu ,  Katherine H CHIANG

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/108

CPC classification number: H01L23/5223 ,  H01L28/90 ,  H01L27/10852 ,  H01L27/10808

Abstract: A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

公开(公告)号：US20250029918A1

公开(公告)日：2025-01-23

申请号：US18909871

申请日：2024-10-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yun-Feng Kao ,  Chien-Hao Huang ,  Gao-Ming Wu ,  Katherine H CHIANG

IPC: H01L23/522 ,  H10B12/00

Abstract: A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.