公开(公告)号：US20240028451A1

公开(公告)日：2024-01-25

申请号：US18230619

申请日：2023-08-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hiroki NOGUCHI ,  Yu-Der CHIH ,  Hsueh-Chih YANG ,  Randy OSBORNE ,  Win San KHWA

IPC分类号： G06F11/10 ,  G11C11/16 ,  G11C29/52

CPC分类号： G06F11/102 ,  G11C11/1655 ,  G11C29/52

摘要： A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

公开(公告)号：US20230063758A1

公开(公告)日：2023-03-02

申请号：US17461532

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Zheng-Jun LIN ,  Pei-Ling TSENG ,  Hsueh-Chih YANG ,  Chung-Cheng CHOU ,  Yu-Der CHIH

IPC分类号： G06F11/10 ,  G11C7/10

摘要： A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.

公开(公告)号：US20220214943A1

公开(公告)日：2022-07-07

申请号：US17703857

申请日：2022-03-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Der CHIH ,  Chia-Fu LEE ,  Chien-Yin LIU ,  Yi-Chun SHIH ,  Kuan-Chun CHEN ,  Hsueh-Chih YANG ,  Shih-Lien Linus LU

IPC分类号： G06F11/10 ,  H03M13/29

摘要： A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

公开(公告)号：US20230236929A1

公开(公告)日：2023-07-27

申请号：US18183679

申请日：2023-03-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Zheng-Jun LIN ,  Pei-Ling TSENG ,  Hsueh-Chih YANG ,  Chung-Cheng CHOU ,  Yu-Der CHIH

IPC分类号： G06F11/10 ,  G11C7/10

CPC分类号： G06F11/1068 ,  G11C7/1096 ,  H03K19/20

摘要： A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

公开(公告)号：US20200174883A1

公开(公告)日：2020-06-04

申请号：US16786795

申请日：2020-02-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Der CHIH ,  Chia-Fu LEE ,  Chien-Yin LIU ,  Yi-Chun SHIH ,  Kuan-Chun CHEN ,  Hsueh-Chih YANG ,  Shih-Lien Linus LU

IPC分类号： G06F11/10 ,  H03M13/29

摘要： A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.

公开(公告)号：US20180004602A1

公开(公告)日：2018-01-04

申请号：US15634876

申请日：2017-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Der CHIH ,  Chia-Fu LEE ,  Chien-Yin LIU ,  Yi-Chun SHIH ,  Kuan-Chun CHEN ,  Hsueh-Chih YANG ,  Shih-Lien Linus LU

IPC分类号： G06F11/10 ,  H03M13/29

摘要： A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.