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    STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE
    6.
    发明申请
    STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE 有权

    公开(公告)号：US20220270681A1

    公开(公告)日：2022-08-25

    申请号：US17185189

    申请日：2021-02-25

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hiroki NOGUCHI ,  Ku-Feng LIN

    IPC分类号： G11C13/00

    摘要： A memory device is disclosed. The memory device includes at least one reference cell and multiple sense amplifiers. The at least one reference cell having a first terminal coupled to a ground. Each of the sense amplifiers has a first terminal and a second terminal. The first terminal is coupled to one of multiple first data lines, and the second terminal is coupled to a second terminal of the at least one reference cell.

    MEMORY INTERFACE
    8.
    发明公开
    MEMORY INTERFACE 审中-公开

    公开(公告)号：US20230221892A1

    公开(公告)日：2023-07-13

    申请号：US17724182

    申请日：2022-04-19

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hiroki NOGUCHI ,  Yih WANG

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    摘要： A memory interface circuit includes a request decoder configured to receive a command signal and an address signal. The request decoder is configured to decode the command signal and the address signal to generate a data count signal and a start address signal. A burst counter is coupled to the request decoder, and the burst counter is configured to update the data count signal after each access of a memory. An address generator is coupled to the request decoder. The address generator is configured to receive the start address signal and generate a subsequent memory address signal based on the start address signal after each access of the memory.

    ONE-TIME-PROGRAMMABLE MEMORY
    9.
    发明申请
    ONE-TIME-PROGRAMMABLE MEMORY 有权

    公开(公告)号：US20220084611A1

    公开(公告)日：2022-03-17

    申请号：US17536639

    申请日：2021-11-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yih WANG ,  Hiroki NOGUCHI

    IPC分类号： G11C17/12 ,  G11C17/16 ,  H01L21/8234 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074

    摘要： Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.

    ONE-TIME-PROGRAMMABLE MEMORY
    10.
    发明申请
    ONE-TIME-PROGRAMMABLE MEMORY 有权

    公开(公告)号：US20210272642A1

    公开(公告)日：2021-09-02

    申请号：US16803202

    申请日：2020-02-27

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hiroki NOGUCHI ,  Yih WANG

    IPC分类号： G11C17/12 ,  G11C17/16 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  H01L21/8234

    摘要： Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.