公开(公告)号：US11844286B2

公开(公告)日：2023-12-12

申请号：US17537793

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H10N50/80 ,  H01L23/538 ,  H01L21/768 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H01L21/768 ,  H01L23/5384 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N50/10 ,  H10N70/011 ,  H10N70/20 ,  H10N70/841 ,  H10N70/8833

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US20220085280A1

公开(公告)日：2022-03-17

申请号：US17537793

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L23/538 ,  H01L43/12 ,  H01L27/22 ,  H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L43/08

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US20220093849A1

公开(公告)日：2022-03-24

申请号：US17537830

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L23/538 ,  H01L43/12 ,  H01L27/22 ,  H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L43/08

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US11751485B2

公开(公告)日：2023-09-05

申请号：US17537830

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H10N50/80 ,  H01L23/538 ,  H01L21/768 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H01L21/768 ,  H01L23/5384 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N50/10 ,  H10N70/011 ,  H10N70/20 ,  H10N70/841 ,  H10N70/8833

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.