公开(公告)号：US20240188454A1

公开(公告)日：2024-06-06

申请号：US18443368

申请日：2024-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B63/00 ,  H10B63/30 ,  H10N70/011 ,  H10N70/063 ,  H10N70/066 ,  H10N70/24 ,  H10N70/801 ,  H10N70/826 ,  H10N70/8833

Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

公开(公告)号：US11889705B2

公开(公告)日：2024-01-30

申请号：US17392555

申请日：2021-08-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10B10/10 ,  H10B99/00 ,  H10N70/00

CPC classification number: H10B63/80 ,  H01L23/528 ,  H01L23/5226 ,  H10B10/10 ,  H10B63/30 ,  H10B99/00 ,  H10N70/021 ,  H10N70/063 ,  H10N70/826 ,  H10N70/8833

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.

公开(公告)号：US11751485B2

公开(公告)日：2023-09-05

申请号：US17537830

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H10N50/80 ,  H01L23/538 ,  H01L21/768 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H01L21/768 ,  H01L23/5384 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N50/10 ,  H10N70/011 ,  H10N70/20 ,  H10N70/841 ,  H10N70/8833

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US20220373594A1

公开(公告)日：2022-11-24

申请号：US17882827

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang

IPC: G01R31/28 ,  G11C29/56 ,  G11C11/16

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

公开(公告)号：US20220093687A1

公开(公告)日：2022-03-24

申请号：US17542638

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Chieh Yang ,  Chih-Yang Chang ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

公开(公告)号：US11249131B2

公开(公告)日：2022-02-15

申请号：US16837906

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Harry-Hak-Lay Chuang ,  Tien-Wei Chiang ,  Chia Yu Wang ,  Meng-Chun Shih ,  Ching-Huang Wang ,  Chih-Yang Chang ,  Chia-Hsiang Chen ,  Chih-Hui Weng

IPC: G01R31/02 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66

Abstract: A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.

公开(公告)号：US10103200B2

公开(公告)日：2018-10-16

申请号：US15292964

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.

Inventor： Chin-Chieh Yang ,  Hsia-Wei Chen ,  Chih-Yang Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/78

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer. The resistive element further includes first and second electrodes interposed by the resistive material layer. The resistive element further includes a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes asymmetric source and drain, the drain having a higher doping concentration than the source. The resistive memory element is coupled with the drain.

公开(公告)号：US20180138403A1

公开(公告)日：2018-05-17

申请号：US15852333

申请日：2017-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

公开(公告)号：US09537094B2

公开(公告)日：2017-01-03

申请号：US14985102

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract translation: 一种存储单元和方法，包括通过第一电介质层中的第一开口形成的第一电极，形成在第一电极上的电阻层，形成在电阻层上的间隔层，形成在电阻层上的第二电极，以及第二电极 形成在第二电极上的电介质层，第二电介质层包括第二开口。 形成在包括第一金属层的基板上的第一电介质层。 第一电极和电阻层共同地包括第一距离超过第一开口延伸的第一唇缘区域。 第二电极和第二电介质层共同包括延伸第二距离超过第一开口的第二唇缘区域。 间隔层从第二距离延伸到第一距离。 使用延伸穿过第二开口的通孔将第二电极耦合到第二金属层。

公开(公告)号：US20160225988A1

公开(公告)日：2016-08-04

申请号：US15094371

申请日：2016-04-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chi Tu ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Yu-Wen Liao ,  Chin-Chieh Yang ,  Wen-Ting Chu

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1616 ,  H01L45/1675

Abstract: A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric.

Abstract translation: 一种方法包括在导电结构上形成保护材料，该结构上的开口部分地填充有第一电极材料以形成第一电极; 电阻变化层和第二电极材料也形成在开口中。 将第二电极材料和电阻变化层图案化以形成存储元件。 所述方法包括在所述存储元件和所述基板的外围区域上形成层间电介质，并且在所述层间电介质中设置触点。