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公开(公告)号：US11894267B2
公开(公告)日：2024-02-06
申请号：US17141852
申请日：2021-01-05
发明人： Hsia-Wei Chen , Fu-Ting Sung , Yu-Wen Liao , Wen-Ting Chu , Fa-Shen Jiang , Tzu-Hsuan Yeh
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76832 , H01L23/528 , H01L23/53209
摘要： A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.
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公开(公告)号：US11889705B2
公开(公告)日：2024-01-30
申请号：US17392555
申请日：2021-08-03
发明人： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC分类号： H01L23/522 , H01L23/528 , H10B63/00 , H10B10/10 , H10B99/00 , H10N70/00
CPC分类号： H10B63/80 , H01L23/528 , H01L23/5226 , H10B10/10 , H10B63/30 , H10B99/00 , H10N70/021 , H10N70/063 , H10N70/826 , H10N70/8833
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.
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公开(公告)号：US11839090B2
公开(公告)日：2023-12-05
申请号：US17342731
申请日：2021-06-09
发明人： Hsia-Wei Chen , Wen-Ting Chu , Yu-Wen Liao
摘要： Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
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公开(公告)号：US11751485B2
公开(公告)日：2023-09-05
申请号：US17537830
申请日：2021-11-30
发明人： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC分类号： H10N50/80 , H01L23/538 , H01L21/768 , H10B61/00 , H10B63/00 , H10N50/01 , H10N50/10 , H10N70/00 , H10N70/20
CPC分类号： H10N50/80 , H01L21/768 , H01L23/5384 , H10B61/22 , H10B63/30 , H10N50/01 , H10N50/10 , H10N70/011 , H10N70/20 , H10N70/841 , H10N70/8833
摘要： Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
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公开(公告)号：US20220093687A1
公开(公告)日：2022-03-24
申请号：US17542638
申请日：2021-12-06
发明人： Chin-Chieh Yang , Chih-Yang Chang , Wen-Ting Chu , Yu-Wen Liao
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.
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公开(公告)号：US10103200B2
公开(公告)日：2018-10-16
申请号：US15292964
申请日：2016-10-13
发明人： Chin-Chieh Yang , Hsia-Wei Chen , Chih-Yang Chang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC分类号： H01L27/24 , H01L29/66 , H01L45/00 , H01L21/265 , H01L21/266 , H01L29/08 , H01L29/78
摘要： A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer. The resistive element further includes first and second electrodes interposed by the resistive material layer. The resistive element further includes a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes asymmetric source and drain, the drain having a higher doping concentration than the source. The resistive memory element is coupled with the drain.
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公开(公告)号：US20180138403A1
公开(公告)日：2018-05-17
申请号：US15852333
申请日：2017-12-22
发明人： Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1666 , H01L45/1675
摘要： A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
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公开(公告)号：US09537094B2
公开(公告)日：2017-01-03
申请号：US14985102
申请日：2015-12-30
发明人： Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1666 , H01L45/1675
摘要： A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
摘要翻译： 一种存储单元和方法，包括通过第一电介质层中的第一开口形成的第一电极，形成在第一电极上的电阻层，形成在电阻层上的间隔层，形成在电阻层上的第二电极，以及第二电极 形成在第二电极上的电介质层，第二电介质层包括第二开口。 形成在包括第一金属层的基板上的第一电介质层。 第一电极和电阻层共同地包括第一距离超过第一开口延伸的第一唇缘区域。 第二电极和第二电介质层共同包括延伸第二距离超过第一开口的第二唇缘区域。 间隔层从第二距离延伸到第一距离。 使用延伸穿过第二开口的通孔将第二电极耦合到第二金属层。
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公开(公告)号：US20160225988A1
公开(公告)日：2016-08-04
申请号：US15094371
申请日：2016-04-08
发明人： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang , Wen-Ting Chu
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L45/08 , H01L45/1253 , H01L45/1616 , H01L45/1675
摘要： A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric.
摘要翻译： 一种方法包括在导电结构上形成保护材料，该结构上的开口部分地填充有第一电极材料以形成第一电极; 电阻变化层和第二电极材料也形成在开口中。 将第二电极材料和电阻变化层图案化以形成存储元件。 所述方法包括在所述存储元件和所述基板的外围区域上形成层间电介质，并且在所述层间电介质中设置触点。
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公开(公告)号：US09368722B2
公开(公告)日：2016-06-14
申请号：US14019857
申请日：2013-09-06
发明人： Sheng-Hung Shih , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Chih-Yang Chang , Chin-Chieh Yang , Hsia-Wei Chen , Wen-Chun You , Chih-Ming Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/146 , H01L45/1608
摘要： One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm.
摘要翻译： 本公开的一个实施例提供了电阻随机存取存储器（RRAM）中的电阻器。 电阻器包括第一电极; 第一电极上的电阻层; 电阻层中的电场增强阵列; 和电阻层上的第二电极。 电场增强阵列包括布置在同一平面中的多个电场增强器。 本公开的一个实施例提供了一种在RRAM中制造电阻器结构的方法。 该方法包括：（1）在第一电极上形成第一电阻层; （2）在电阻层上形成金属层; （3）图案化金属层以在电阻层上形成金属点阵列; 和（4）在金属点阵上形成第二电极。 金属点阵列包括多个金属点，相邻金属点之间的距离小于40nm。
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