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公开(公告)号：US20220157889A1
公开(公告)日：2022-05-19
申请号：US17589278
申请日：2022-01-31
Inventor： Chin-Chieh Yang , Hsia-Wei Chen , Chih-Yang Chang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L27/24 , H01L29/66 , H01L45/00 , H01L21/265 , H01L21/266 , H01L29/08 , H01L29/78
Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
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公开(公告)号：US20220093849A1
公开(公告)日：2022-03-24
申请号：US17537830
申请日：2021-11-30
Inventor： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC: H01L43/02 , H01L23/538 , H01L43/12 , H01L27/22 , H01L45/00 , H01L21/768 , H01L27/24 , H01L43/08
Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
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公开(公告)号：US20200381622A1
公开(公告)日：2020-12-03
申请号：US16994359
申请日：2020-08-14
Inventor： Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L45/00
Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
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公开(公告)号：US10749108B2
公开(公告)日：2020-08-18
申请号：US16217134
申请日：2018-12-12
Inventor： Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L45/00
Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
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公开(公告)号：US10103330B2
公开(公告)日：2018-10-16
申请号：US15811249
申请日：2017-11-13
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang , Wen-Ting Chu
Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.
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Patent Agency Ranking
公开(公告)号：US10038139B2
公开(公告)日：2018-07-31
申请号：US15144639
申请日：2016-05-02
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chin-Chieh Yang , Chih-Yang Chang , Yu-Wen Liao
CPC classification number: H01L45/1246 , H01L27/2436 , H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.
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公开(公告)号：US09818938B2
公开(公告)日：2017-11-14
申请号：US14844207
申请日：2015-09-03
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang , Wen-Ting Chu
CPC classification number: H01L45/1253 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/124 , H01L45/14 , H01L45/146 , H01L45/1608 , H01L45/1675
Abstract: A method of forming a semiconductor structure includes depositing a first electrode material over a conductive structure and a dielectric layer, patterning the first electrode material to form a first electrode contacting the conductive structure, depositing a resistance variable layer over the first electrode and the dielectric layer, depositing a second electrode material over the resistance variable layer, and etching a portion of the second electrode material and the resistance variable layer to form a second electrode over a remaining portion of the resistance variable layer.
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8.发明申请One Transistor and One Resistive Random Access Memory (RRAM) Structure with Spacer 审中-公开一个晶体管和一个电阻随机存取存储器（RRAM）结构与间隔器公开(公告)号：US20160248008A1
公开(公告)日：2016-08-25
申请号：US15144639
申请日：2016-05-02
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chin-Chieh Yang , Chih-Yang Chang , Yu-Wen Liao
CPC classification number: H01L45/1246 , H01L27/2436 , H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.
Abstract translation: 本公开提供了一种电阻随机存取存储器（RRAM）单元及其制造方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和顶部部分的底部电极，底部电极上的电阻材料层具有与底部电极的顶部部分的宽度相同的宽度; 底部电极上的覆盖层; 包围覆盖层的间隔物; 并且所述覆盖层上的顶部电极具有比所述电阻材料层更小的宽度。 RRAM单元还包括将RRAM结构的顶部电极连接到金属层的导电材料。
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公开(公告)号：US09312482B2
公开(公告)日：2016-04-12
申请号：US13896064
申请日：2013-05-16
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang , Wen-Ting Chu
CPC classification number: H01L45/146 , H01L45/08 , H01L45/1253 , H01L45/1616 , H01L45/1675
Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer.
Abstract translation: 半导体结构包括存储区。 存储器结构设置在存储器区域上。 存储结构包括第一电极，电阻变化层，保护材料和第二电极。 第一电极在存储区域上具有顶表面。 电阻变化层具有至少第一部分和第二部分。 第一部分设置在第一电极的顶表面上，第二部分从第一部分向上延伸。 保护材料围绕电阻变化层的第二部分。 保护材料可配置为保护电阻变化层中的至少一个导电路径。 第二电极设置在电阻变化层上。
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公开(公告)号：US08921818B2
公开(公告)日：2014-12-30
申请号：US13673658
申请日：2012-11-09
Inventor： Kuo-Chi Tu , Wen-Ting Chu , Chin-Chieh Yang , Yu-Wen Liao , Hsia-Wei Chen , Chih-Yang Chang
CPC classification number: H01L45/146 , H01L45/08 , H01L45/1226 , H01L45/1691
Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.
Abstract translation: 半导体结构包括电阻变化存储器结构。 半导体结构还包括电介质层。 电阻可变存储器结构在电介质层之上。 电阻可变存储器结构包括设置在电介质层上的第一电极。 第一电极具有侧壁表面。 电阻变化层具有设置在第一电极的侧壁表面上的第一部分和从第一部分延伸离开第一电极的第二部分。 第二电极在电阻变化层之上。
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