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公开(公告)号：US20220352179A1
公开(公告)日：2022-11-03
申请号：US17514118
申请日：2021-10-29
发明人： Chih-Chuan Yang , Kuo-Hsiu Hsu , Chia-Hao Pao , Shih-Hao Lin
IPC分类号： H01L27/11 , G11C11/412 , G11C11/417
摘要： A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.
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公开(公告)号：US11444197B2
公开(公告)日：2022-09-13
申请号：US16785247
申请日：2020-02-07
IPC分类号： H01L29/78 , H01L29/06 , H01L29/417 , H01L27/088 , H01L29/66 , H01L29/16
摘要： A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.
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公开(公告)号：US20210249530A1
公开(公告)日：2021-08-12
申请号：US16785247
申请日：2020-02-07
IPC分类号： H01L29/78 , H01L29/06 , H01L29/417 , H01L29/16 , H01L29/66 , H01L27/088
摘要： A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.
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公开(公告)号：US12087633B2
公开(公告)日：2024-09-10
申请号：US17464398
申请日：2021-09-01
发明人： Chih-Chuan Yang , Chia-Hao Pao , Kuo-Hsiu Hsu , Shih-Hao Lin , Shang-Rong Li , Ping-Wei Wang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823412
摘要： A method of forming a semiconductor structure includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, forming cladding layers along sidewalls of the fin structure, forming a dummy gate stack over the cladding layers, and forming source/drain (S/D) features in the fin structure and adjacent to the dummy gate stack. The method further includes removing the dummy gate stack to form a gate trench adjacent to the S/D features, removing the cladding layers to form first openings along the sidewalls of the fin structure, where the first openings extend to below the stack, removing the first semiconductor layers to form second openings between the second semiconductor layers and adjacent to the first openings, and subsequently forming a metal gate stack in the gate trench, the first openings, and the second openings.
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公开(公告)号：US12016169B2
公开(公告)日：2024-06-18
申请号：US17842208
申请日：2022-06-16
发明人： Ping-Wei Wang , Lien Jung Hung , Kuo-Hsiu Hsu , Kian-Long Lim , Yu-Kuan Lin , Chia-Hao Pao , Chih-Chuan Yang , Shih-Hao Lin , Choh Fei Yeap
IPC分类号： H01L23/528 , G11C11/412 , G11C11/419 , H01L21/66 , H04N21/426 , H10B10/00 , H10B41/35
CPC分类号： H10B10/12 , G11C11/412 , G11C11/419 , H01L22/12 , H01L23/528 , H04N21/42692 , H10B10/00 , H10B41/35 , G11C2213/74 , G11C2213/79 , H01L2924/1437
摘要： A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.
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公开(公告)号：US11996338B2
公开(公告)日：2024-05-28
申请号：US18342919
申请日：2023-06-28
发明人： Jing-Yi Lin , Chih-Chuan Yang , Kuo-Hsiu Hsu , Lien-Jung Hung
CPC分类号： H01L22/32 , G01R31/2884
摘要： A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.
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公开(公告)号：US20220310630A1
公开(公告)日：2022-09-29
申请号：US17842208
申请日：2022-06-16
发明人： Ping-Wei Wang , Lien Jung Hung , Kuo-Hsiu Hsu , Kian-Long Lim , Yu-Kuan Lin , Chia-Hao Pao , Chih-Chuan Yang , Shih-Hao Lin , Choh Fei Yeap
IPC分类号： H01L27/11 , G11C11/412 , G11C11/419 , H01L21/66 , H01L23/528 , H01L27/11524 , H04N21/426
摘要： A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
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公开(公告)号：US12046276B2
公开(公告)日：2024-07-23
申请号：US18306757
申请日：2023-04-25
发明人： Chih-Chuan Yang , Feng-Ming Chang , Kuo-Hsiu Hsu , Ping-Wei Wang
IPC分类号： G11C11/412 , H10B10/00
CPC分类号： G11C11/412 , H10B10/12
摘要： One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.
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9.发明公开公开(公告)号：US20230371225A1
公开(公告)日：2023-11-16
申请号：US18358562
申请日：2023-07-25
发明人： Ping-Wei Wang , Lien-Jung Hung , Kuo-Hsiu Hsu , Kian-Long Lim , Yu-Kuan LIN , Chia-Hao Pao , Chih-Chuan Yang , Shih-Hao Lin , Choh Fei Yeap
IPC分类号： H01L23/528 , G11C11/412 , G11C11/419 , H01L21/66 , H04N21/426
CPC分类号： H10B10/12 , H01L23/528 , G11C11/412 , G11C11/419 , H10B10/00 , H01L22/12 , H10B41/35 , H04N21/42692 , H01L2924/1437 , G11C2213/79 , G11C2213/74
摘要： A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
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公开(公告)号：US10833090B2
公开(公告)日：2020-11-10
申请号：US16397353
申请日：2019-04-29
发明人： Feng-Ming Chang , Kuo-Hsiu Hsu
IPC分类号： H01L27/11 , H01L27/02 , H01L21/768 , H01L23/485 , H01L21/8239
摘要： Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.
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