公开(公告)号：US11777016B2

公开(公告)日：2023-10-03

申请号：US17811266

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Yu-Kuan Lin ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/40 ,  H01L23/00 ,  H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H10B10/00

CPC classification number: H01L29/66795 ,  H01L23/5286 ,  H01L24/83 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696 ,  H10B10/00 ,  H01L2029/7858 ,  H01L2224/83097 ,  H01L2224/83099 ,  H01L2224/83896

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

公开(公告)号：US20220336641A1

公开(公告)日：2022-10-20

申请号：US17811266

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pei-Wei Wang ,  Chih-Chuan Yang ,  Yu-Kuan Lin ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/40 ,  H01L23/00 ,  H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

公开(公告)号：US12016169B2

公开(公告)日：2024-06-18

申请号：US17842208

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Lien Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan Lin ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC: H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H04N21/426 ,  H10B10/00 ,  H10B41/35

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H01L22/12 ,  H01L23/528 ,  H04N21/42692 ,  H10B10/00 ,  H10B41/35 ,  G11C2213/74 ,  G11C2213/79 ,  H01L2924/1437

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.

公开(公告)号：US20220310630A1

公开(公告)日：2022-09-29

申请号：US17842208

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Lien Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan Lin ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H01L23/528 ,  H01L27/11524 ,  H04N21/426

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

公开(公告)号：US20230371225A1

公开(公告)日：2023-11-16

申请号：US18358562

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Ping-Wei Wang ,  Lien-Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan LIN ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC: H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H04N21/426

CPC classification number: H10B10/12 ,  H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H10B10/00 ,  H01L22/12 ,  H10B41/35 ,  H04N21/42692 ,  H01L2924/1437 ,  G11C2213/79 ,  G11C2213/74

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

公开(公告)号：US12040383B2

公开(公告)日：2024-07-16

申请号：US17465762

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Lin Lee ,  Choh Fei Yeap ,  Da-Wen Lin ,  Chih-Chieh Yeh

IPC: H01L29/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/764 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/0259 ,  H01L21/28123 ,  H01L21/764 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78621 ,  H01L29/78696

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

公开(公告)号：US11411100B2

公开(公告)日：2022-08-09

申请号：US17037274

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Yu-Kuan Lin ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/40 ,  H01L23/00 ,  H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L29/423 ,  H01L29/775

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

公开(公告)号：US20220102535A1

公开(公告)日：2022-03-31

申请号：US17037274

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pei-Wei Wang ,  Chih-Chuan Yang ,  Yu-Kuan Lin ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/40 ,  H01L23/00 ,  H01L27/11 ,  H01L29/78 ,  H01L29/417 ,  H01L23/528

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.