公开(公告)号：US10354920B2

公开(公告)日：2019-07-16

申请号：US15231215

申请日：2016-08-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC分类号： H01L27/07 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02 ,  H01L29/40

摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

公开(公告)号：US10720361B2

公开(公告)日：2020-07-21

申请号：US16512041

申请日：2019-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC分类号： H01L27/07 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02 ,  H01L29/94 ,  H01L29/40

摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

公开(公告)号：US09337293B2

公开(公告)日：2016-05-10

申请号：US13774470

申请日：2013-02-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pai-Chieh Wang ,  Tsung Yao Wen ,  Jyh-Huei Chen

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及具有电极的半导体器件。 半导体器件的示例性结构包括半导体衬底; 在所述半导体衬底上的电极，其中所述电极包括在所述电极的上部中的沟槽; 以及沟槽中的电介质特征。

公开(公告)号：US20140239417A1

公开(公告)日：2014-08-28

申请号：US13774470

申请日：2013-02-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pai-Chieh Wang ,  Tsung Yao Wen ,  Jyh-Huei Chen

IPC分类号： H01L29/49 ,  H01L29/40

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及具有电极的半导体器件。 半导体器件的示例性结构包括半导体衬底; 在所述半导体衬底上的电极，其中所述电极包括在所述电极的上部中的沟槽; 以及沟槽中的电介质特征。

公开(公告)号：US20190341310A1

公开(公告)日：2019-11-07

申请号：US16512041

申请日：2019-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC分类号： H01L21/822 ,  H01L29/40 ,  H01L49/02 ,  H01L27/08 ,  H01L27/07 ,  H01L29/94 ,  H01L21/8234 ,  H01L27/06

摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

公开(公告)号：US09941372B2

公开(公告)日：2018-04-10

申请号：US15149773

申请日：2016-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pai-Chieh Wang ,  Tsung Yao Wen ,  Jyh-Huei Chen

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L29/40

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.

公开(公告)号：US20160351451A1

公开(公告)日：2016-12-01

申请号：US15231215

申请日：2016-08-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC分类号： H01L21/822 ,  H01L29/40 ,  H01L27/06

CPC分类号： H01L21/822 ,  H01L21/823437 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/0811 ,  H01L28/20 ,  H01L29/401 ,  H01L29/94

摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.