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公开(公告)号：US20240396749A1
公开(公告)日：2024-11-28
申请号：US18789393
申请日：2024-07-30
Inventor： Katherine H. Chiang , Shih-Lien Linus Lu
IPC: H04L9/32 , G11C11/418 , G11C11/419 , H04L9/06
Abstract: The present disclosure describes embodiments of a device with memory and a processor. The memory is configured to store integrated circuit (IC) trim and redundancy information. The processor is configured to extract bits from the IC trim and redundancy information, perform a hashing function on the extracted bits to generate hashed bits, and in response to statistical properties of the hashed bits meeting one or more criteria, output the hashed bits. In some embodiments, the memory that stores the IC trim and redundancy information can be different from other memory used by the device for other operations (e.g., accessing user data and program data that have been written into system memory).
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公开(公告)号：US12114506B2
公开(公告)日：2024-10-08
申请号：US18357139
申请日：2023-07-23
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
IPC: H10B51/20 , G11C5/06 , G11C11/22 , H01L23/522
CPC classification number: H10B51/20 , G11C5/06 , G11C11/223 , H01L23/5221
Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.
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公开(公告)号：US12089414B2
公开(公告)日：2024-09-10
申请号：US17400081
申请日：2021-08-11
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
CPC classification number: H10B51/20 , G11C5/06 , G11C11/223
Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a multi-layer stack, a plurality of memory cells, and a plurality of conductive contacts. The substrate includes an array region and a staircase region. The multi-layer stack is disposed on the substrate in the array region, wherein the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure. The plurality of memory cells are respectively disposed on sidewalls of the multi-layer stack in the array region, and arranged at least along a stacking direction of the multi-layer stack. The plurality of conductive contacts are respectively on the staircase structure. At least two conductive contacts are electrically connected to each other.
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公开(公告)号：US12080704B2
公开(公告)日：2024-09-03
申请号：US18295134
申请日：2023-04-03
Inventor： Shih-Lien Linus Lu
IPC: G11C11/418 , G11C11/412 , G11C11/419 , H01L27/02 , H10B10/00
CPC classification number: H01L27/0207 , G11C11/412 , G11C11/418 , G11C11/419 , H10B10/00 , H10B10/12
Abstract: A memory circuit includes a first and a second bit line, a first and a second inverter, a P-type pass gate transistor, a pre-charge circuit, a first transmission gate and a sense amplifier. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The pre-charge circuit is coupled to at least the first bit line or the second bit line, and configured to charge at least the first or second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a voltage of a second logical level. The first transmission gate is coupled to the first bit line, and configured to receive a first and a second control signal. The sense amplifier is coupled to the first bit line by the first transmission gate.
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公开(公告)号：US20230189529A1
公开(公告)日：2023-06-15
申请号：US18162642
申请日：2023-01-31
Inventor： Chao-I Wu , Yu-Ming Lin , Shih-Lien Linus Lu , Sai-Hooi Yeong , Bo-Feng Young
Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.
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Patent Agency Ranking
公开(公告)号：US11461525B2
公开(公告)日：2022-10-04
申请号：US16661971
申请日：2019-10-23
Inventor： Cheng-En Lee , Shih-Lien Linus Lu
IPC: G06F30/30 , H01L27/02 , G06F30/392 , G06F30/39 , G06F119/18
Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell arranged in a first column in a first direction and a second PUF cell arranged in a second column in the first direction. The first PUF cell includes a first set of conductive structures extending in the first and a second direction. The second PUF cell includes a second set of conductive structures extending in the first and the second direction. The first PUF cell includes a first conductive structure and a second conductive structure extending in the second direction. The second PUF cell includes a third conductive structure and a fourth conductive structure extending in the second direction. The first and third conductive structure or the second and fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell extending in the second direction.
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公开(公告)号：US20220231051A1
公开(公告)日：2022-07-21
申请号：US17400087
申请日：2021-08-11
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
IPC: H01L27/11597 , H01L23/522 , G11C5/06 , G11C11/22
Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.
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公开(公告)号：US20220231050A1
公开(公告)日：2022-07-21
申请号：US17400081
申请日：2021-08-11
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
IPC: H01L27/11597 , G11C5/06 , G11C11/22
Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a multi-layer stack, a plurality of memory cells, and a plurality of conductive contacts. The substrate includes an array region and a staircase region. The multi-layer stack is disposed on the substrate in the array region, wherein the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure. The plurality of memory cells are respectively disposed on sidewalls of the multi-layer stack in the array region, and arranged at least along a stacking direction of the multi-layer stack. The plurality of conductive contacts are respectively on the staircase structure. At least two conductive contacts are electrically connected to each other.
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9.发明申请公开(公告)号：US20220156189A1
公开(公告)日：2022-05-19
申请号：US17096957
申请日：2020-11-13
Inventor： Shih-Lien Linus Lu
IPC: G06F12/0804 , G06F12/06 , G11C11/4093 , G11C11/4096
Abstract: A memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.
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公开(公告)号：US20220005830A1
公开(公告)日：2022-01-06
申请号：US17228671
申请日：2021-04-12
Inventor： Chao-I Wu , Yu-Ming Lin , Shih-Lien Linus Lu , Sai-Hooi Yeong , Bo-Feng Young
IPC: H01L27/11597 , H01L29/24 , H01L27/1159
Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.
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