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公开(公告)号:US20240222407A1
公开(公告)日:2024-07-04
申请号:US18442357
申请日:2024-02-15
发明人: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Wen-Chang Kuo , Sheng-Chau Chen , Feng-Chi Hung , Sheng-Chan Li
IPC分类号: H01L27/146
CPC分类号: H01L27/1463 , H01L27/14636 , H01L27/14683
摘要: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.
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公开(公告)号:US11494497B2
公开(公告)日:2022-11-08
申请号:US16412753
申请日:2019-05-15
发明人: Wen-Chang Kuo , Chiang Kao , Kuo Hsiung Chen , Ho-Han Liu , Ti-Yen Yang , Jo-Chan Liu , Chi-Pin Wang , Yao-Hsiung Chang
摘要: A method of operating a user device includes: detecting whether the user device is located within a restricted zone by a monitoring entity of the user device; and limiting access to the user device by the monitoring entity in response to detecting the user device as being outside the restricted zone.
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公开(公告)号:US20240088187A1
公开(公告)日:2024-03-14
申请号:US18149240
申请日:2023-01-03
发明人: Chih Cheng Shih , Tsun-Kai Tsao , Jiech-Fun Lu , Hung-Wen Hsu , Bing Cheng You , Wen-Chang Kuo
IPC分类号: H01L27/146
CPC分类号: H01L27/1463 , H01L27/14643 , H01L27/14689
摘要: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.
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公开(公告)号:US11901387B2
公开(公告)日:2024-02-13
申请号:US17369567
申请日:2021-07-07
发明人: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Wen-Chang Kuo , Sheng-Chau Chen , Feng-Chi Hung , Sheng-Chan Li
IPC分类号: H01L27/146 , H01L21/762
CPC分类号: H01L27/1463 , H01L21/76224 , H01L27/14621 , H01L27/14627 , H01L27/14683
摘要: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.
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公开(公告)号:US20220278144A1
公开(公告)日:2022-09-01
申请号:US17369567
申请日:2021-07-07
发明人: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Wen-Chang Kuo , Sheng-Chau Chen , Feng-Chi Hung , Sheng-Chan Li
IPC分类号: H01L27/146 , H01L21/762
摘要: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.
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公开(公告)号:US12001571B2
公开(公告)日:2024-06-04
申请号:US18052211
申请日:2022-11-03
发明人: Wen-Chang Kuo , Chiang Kao , Kuo Hsiung Chen , Ho-Han Liu , Ti-Yen Yang , Jo-Chan Liu , Chi-Pin Wang , Yao-Hsiung Chang
CPC分类号: G06F21/602 , G06F21/32 , H04W48/04
摘要: A method of operating a user device includes: receiving a command from a user to power on the user device, wherein the user device includes information on a restricted zone associated with the user device; detecting, by a monitoring entity of the user device without involvement of any device external to the user device, whether the user device is located within the restricted zone in response to the user device being powered on and before an operating system of the user device is executed; and granting access of the user to the user device by the monitoring entity in response to detecting the user device as being within the restricted zone.
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公开(公告)号:US10727191B2
公开(公告)日:2020-07-28
申请号:US16231844
申请日:2018-12-24
发明人: Gulbagh Singh , Chih-Ming Lee , Chi-Yen Lin , Wen-Chang Kuo , C. C. Liu
IPC分类号: H01L21/00 , H01L29/00 , H01L23/00 , H01L23/522 , H01L23/58 , H01L23/528 , H01L21/78 , H01L29/06 , H01L23/532 , G06F30/392 , G06F30/398 , H01L23/544 , H01L23/31 , H01L21/66 , H01L23/525
摘要: A semiconductor structure includes a first contact pad over a passivation layer, wherein the first contact pad is in a circuit region. The semiconductor structure further includes a plurality of second contact pads over the passivation layer, wherein each second contact pad of the plurality of second contact pads is in a non-circuit region. The semiconductor structure further includes a first buffer layer over the first contact pad and over a first second contact pad of the plurality of second contact pads. The semiconductor structure further includes a second buffer layer over the first buffer layer, the first contact pad, the first second contact pad and a portion of a second second contact pad of the plurality of second contact pads, wherein the second buffer layer exposes a portion of the second second contact pad of the plurality of second contact pads.
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公开(公告)号:US10163831B2
公开(公告)日:2018-12-25
申请号:US15642837
申请日:2017-07-06
发明人: Gulbagh Singh , Chih-Ming Lee , Chi-Yen Lin , Wen-Chang Kuo , C. C. Liu
IPC分类号: H01L21/00 , H01L29/00 , H01L23/00 , H01L23/522 , H01L23/58 , H01L23/528 , H01L21/78 , H01L23/544 , G06F17/50 , H01L29/06 , H01L23/31 , H01L23/532 , H01L21/66
摘要: A method of fabricating a semiconductor device includes forming a first contact pad and a second contact pad over a first passivation layer, depositing a first buffer layer over the first contact pad and the second contact pad, and depositing a second buffer layer over the first buffer layer and the second contact pad. The first contact pad is in a circuit region and the second contact pad is in a non-circuit region. An edge of the second contact pad is exposed and a periphery of the first contact pad and an edge of the second contact pad are covered by the first buffer layer.
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公开(公告)号:US10090392B2
公开(公告)日:2018-10-02
申请号:US14158643
申请日:2014-01-17
发明人: I-Chih Chen , Chih-Mu Huang , Ling-Sung Wang , Ying-Hao Chen , Wen-Chang Kuo , Jung-Chi Jeng
IPC分类号: H01L29/417 , H01L29/08 , H01L29/66 , H01L21/285 , H01L29/78 , H01L29/45 , H01L21/324 , H01L23/485 , H01L29/165 , H01L21/768
摘要: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.
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公开(公告)号:US09865731B2
公开(公告)日:2018-01-09
申请号:US14081517
申请日:2013-11-15
发明人: I-Chih Chen , Ying-Lang Wang , Chih-Mu Huang , Ying-Hao Chen , Wen-Chang Kuo , Jung-Chi Jeng
IPC分类号: H01L27/12 , H01L29/78 , H01L27/092 , H01L21/8238 , H01L21/265 , H01L21/84 , H01L29/161 , H01L29/66
CPC分类号: H01L29/7833 , H01L21/26506 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0928 , H01L29/161 , H01L29/6659
摘要: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.
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