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    Back end of line via to metal line margin improvement
    1.
    发明授权
    Back end of line via to metal line margin improvement 有权

    公开(公告)号：US11276638B2

    公开(公告)日：2022-03-15

    申请号：US16676819

    申请日：2019-11-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. ,  TSMC NANJING COMPANY, LIMITED

    Inventor： Yi-Chun Huang ,  I-Chih Chen ,  Chun-Wei Kuo

    IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: A semiconductor structure includes a first conductive line and a second conductive line in a first dielectric layer, and a third conductive line in a second dielectric layer overlying the first dielectric layer. The first conductive line and the second conductive line each extend along a first direction. The third conductive line extends along a second direction different from the first direction and above at least the second conductive line. The semiconductor structure further includes a via in the second dielectric layer and electrically connecting the second conductive line and the third conductive line. The via lands on a portion of the second conductive line. The semiconductor structure further includes a dielectric cap over the first conductive line. A bottom surface of the dielectric cap is below a top surface of the first dielectric layer.

    Semiconductor device structure and manufacturing method thereof
    7.
    发明授权
    Semiconductor device structure and manufacturing method thereof 有权
    半导体器件结构及其制造方法

    公开(公告)号：US09450093B2

    公开(公告)日：2016-09-20

    申请号：US14515225

    申请日：2014-10-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： I-Chih Chen ,  Chih-Ming Hsieh ,  Fu-Tsun Tsai ,  Yung-Fa Lee ,  Chih-Mu Huang

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324

    CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/324 ,  H01L29/7848 ,  H01L29/785

    Abstract: Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between isolation regions, and a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a gate spacer of the gate structure; patterning the fin structure to comprise a pattern of at least one upward step rising from the isolation region; forming a capping layer over the fin structure, the isolation region, and the gate structure; performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and removing the capping layer.

    Abstract translation: 本公开的一些实施例提供一种制造半导体器件的方法，该半导体器件包括接收包括形成在隔离区域之间的鳍结构的FinFET前体，以及形成在鳍结构的一部分上的栅极结构，使得翅片结构的侧壁处于 与栅极结构的栅极间隔物接触; 图案化鳍结构以包括从隔离区域上升的至少一个向上步骤的图案; 在鳍结构，隔离区和栅结构之上形成覆盖层; 对FinFET前体进行退火处理以沿着向上的台阶形成至少两个位错; 并去除覆盖层。

    PAD STRUCTURE LAYOUT FOR SEMICONDUCTOR DEVICE
    9.
    发明申请
    PAD STRUCTURE LAYOUT FOR SEMICONDUCTOR DEVICE 有权
    半导体器件的PAD结构布局

    公开(公告)号：US20150001658A1

    公开(公告)日：2015-01-01

    申请号：US13929172

    申请日：2013-06-27

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shang-Yen Wu ,  I-Chih Chen ,  Yi-Sheng Liu ,  Volume Chien ,  Fu-Tsun Tsai ,  Chi-Cherng Jeng ,  Ying-Hao Chen

    IPC: H01L31/02

    CPC classification number: H01L27/1464 ,  H01L24/05 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.

    Abstract translation: 提供了一种包括设置在基板上的光感测区域的半导体器件，其包括在衬垫元件下方具有一个或多个图案化层的接合结构。 焊盘元件可以耦合到光感测区域，并且可以形成在设置在衬底上的第一金属层中。 器件的第二金属层具有第一结合区域，第二金属层的位于衬垫元件下面的区域。 第二金属层的该第一接合区域包括插入介电体的多个导电线图案。 通孔连接垫元件和第二金属层。

    Method of back end of line via to metal line margin improvement
    10.
    发明授权
    Method of back end of line via to metal line margin improvement 有权

    公开(公告)号：US12255134B2

    公开(公告)日：2025-03-18

    申请号：US17667488

    申请日：2022-02-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

    Inventor： Yi-Chun Huang ,  I-Chih Chen ,  Chun-Wei Kuo

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: A method of forming a semiconductor structure includes forming a plurality of lower level conductive lines in a first dielectric layer. The plurality of lower level conductive lines includes a first lower level conductive line. The method further includes recessing portions of the first lower level conductive line below a top surface of the first dielectric layer to form a recess, forming a dielectric cap in the recess, depositing a second dielectric layer over the first dielectric layer. Forming a via opening exposes a portion of the second lower level conductive line. The method further includes forming an upper level conductive line and a via in the trench and in the via opening, respectively. The via couples the upper level conductive line to the second lower level conductive line, and the upper level conductive line overlaps with the dielectric cap.

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