公开(公告)号：US12046506B2

公开(公告)日：2024-07-23

申请号：US17382873

申请日：2021-07-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hsin Chan ,  Cai-Ling Wu ,  Chang-Wen Chen ,  Po-Hsiang Huang ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Jr-Hung Li ,  Jay Chiu ,  Ting-Kui Chang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417

CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53295 ,  H01L29/41725

摘要： In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

公开(公告)号：US20230411144A1

公开(公告)日：2023-12-21

申请号：US17841679

申请日：2022-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Han Chen ,  Hung-Chun Chen ,  Yuan-Chun Chien ,  Wei Tse Hsu ,  Yu-Yu Chen ,  Chien-Chih Chiu

IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/768

CPC分类号： H01L21/02178 ,  H01L21/31053 ,  H01L21/02425 ,  H01L21/76829

摘要： A method for forming a semiconductor device includes followings. A metal layer is formed to embedded in a first dielectric layer. An etch stop layer is formed over the metal layer and the first dielectric layer. A second dielectric layer is formed over the etch stop layer. A portion of the second dielectric layer is removed to expose a portion of the etch stop layer and to form a via by a dry etching process. The portion of the etch stop layer exposed by the second dielectric layer is removed to expose the metal layer and to form a damascene cavity by a wet etching process. A damascene structure is formed in the damascene cavity.

公开(公告)号：US10056258B2

公开(公告)日：2018-08-21

申请号：US15723688

申请日：2017-10-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yan-Jhi Huang ,  Yu-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/768

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76816

摘要： A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer and the merge cut feature. The first mandrel layer is patterned to form first openings therein. First spacers are formed on sidewalls of the first openings. The first openings are filled with a dielectric material to form plugs. The first mandrel layer is patterned to remove portions of the first mandrel layer interposed between adjacent first spacers. The merge cut feature is patterned using the first spacers and the plugs as a combined mask. The plugs are removed. The mask layer is patterned using the first spacers as a mask. The target layer is patterned, using the mask layer and the merge cut feature as a combined mask, to form second openings therein.

公开(公告)号：US20240021468A1

公开(公告)日：2024-01-18

申请号：US18446217

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hsin Chan ,  Cai-Ling Wu ,  Chang-Wen Chen ,  Po-Hsiang Huang ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Jr-Hung Li ,  Jay Chiu ,  Ting-Kui Chang

IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L29/41725 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/5222 ,  H01L23/53295 ,  H01L21/76885 ,  H01L21/7688 ,  H01L21/76831 ,  H01L21/76834

摘要： In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

公开(公告)号：US20200075405A1

公开(公告)日：2020-03-05

申请号：US16679940

申请日：2019-11-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Wei Huang ,  Cheng-Li Fan ,  Yu-Yu Chen

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033 ,  H01L23/535

摘要： A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.

公开(公告)号：US11852982B2

公开(公告)日：2023-12-26

申请号：US17835152

申请日：2022-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yuan Yao ,  Yu-Yu Chen ,  Hsiang-Lung Tsou

IPC分类号： G03F7/20 ,  G03F7/00 ,  B08B5/00 ,  B08B6/00

CPC分类号： G03F7/70741 ,  B08B5/00 ,  B08B6/00

摘要： A semiconductor manufacturing system includes a semiconductor processing apparatus. The semiconductor processing apparatus includes a processing chamber configured to perform a semiconductor process on a semiconductor wafer, and a transferring module configured to transfer the semiconductor wafer into and out of the processing chamber. The semiconductor manufacturing system also includes a particle attracting member. The semiconductor manufacturing system also includes a monitoring device configured to control the transferring module to load the particle attracting member into the processing chamber in a cleaning cycle while the semiconductor wafer is not in the processing chamber, and control the transferring module to load the particle attracting member out of the processing chamber after the cleaning cycle. In the cleaning cycle, particles in the processing chamber are attracted to the surface of a coating layer of the particle attracting member due to the potential difference between the coating layer and the particles.

公开(公告)号：US20230335433A1

公开(公告)日：2023-10-19

申请号：US18339264

申请日：2023-06-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Nien Su ,  Yu-Yu Chen

IPC分类号： H01L21/768 ,  H01L21/033

CPC分类号： H01L21/76816 ,  H01L21/0335 ,  H01L21/76877 ,  H01L21/0338 ,  H01L21/0337

摘要： In some embodiments, the present disclosure relates to a method that includes depositing multiple hard mask layers over an interconnect dielectric layer. A first patterning layer is deposited over the multiple hard mask layers, and a first masking structure is formed over the first masking structure. The first masking structure has openings formed by a first extreme ultraviolet (EUV) lithography process. Portions of the first patterning layer are removed according to the first masking structure. A second masking structure is formed within the patterned first patterning layer. A third masking structure is formed over a topmost one of the hard mask layers and has openings formed by a second EUV lithography process. Removal processes are performed to pattern the multiple hard mask layers to form openings in the interconnect dielectric layer, and interconnect wires having rounded corners are formed within the openings of the interconnect dielectric layer.

公开(公告)号：US20220359263A1

公开(公告)日：2022-11-10

申请号：US17382873

申请日：2021-07-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hsin Chan ,  Cai-Ling Wu ,  Chang-Wen Chen ,  Po-Hsiang Huang ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Jr-Hung Li ,  Jay Chiu ,  Ting-Kui Chang

IPC分类号： H01L21/768 ,  H01L29/417

摘要： In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

公开(公告)号：US10475700B2

公开(公告)日：2019-11-12

申请号：US15726035

申请日：2017-10-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Wei Huang ,  Cheng-Li Fan ,  Yu-Yu Chen

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

摘要： A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.

公开(公告)号：US10170307B1

公开(公告)日：2019-01-01

申请号：US15665682

申请日：2017-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Wei Huang ,  Yu-Yu Chen

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/3213 ,  G03F7/09 ,  H01L21/28

摘要： A semiconductor device and method includes a method. The method includes patterning a plurality of first mandrels over a first mask layer. The method further includes forming a first spacer layer on sidewalls and tops of the first mandrels. The method further includes removing horizontal portions of the first spacer layer, with remaining vertical portions of the first spacer layer forming first spacers. The method further includes, after removing the horizontal portions of the first spacer layer, depositing a reverse material between the first spacers. The method further includes patterning the first mask layer using the first spacers and the reverse material in combination as a first etching mask.