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公开(公告)号:US11437386B2
公开(公告)日:2022-09-06
申请号:US16786499
申请日:2020-02-10
发明人: Meng-Sheng Chang , Chia-En Huang , Shao-Yu Chou , Yih Wang
IPC分类号: H01L27/112 , H01L23/528 , H01L23/532 , G11C17/16 , G06F30/392 , H01L23/525 , G11C17/18
摘要: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.
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公开(公告)号:US10991442B2
公开(公告)日:2021-04-27
申请号:US17013967
申请日:2020-09-08
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US10803967B2
公开(公告)日:2020-10-13
申请号:US16830429
申请日:2020-03-26
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US20190019565A1
公开(公告)日:2019-01-17
申请号:US16133783
申请日:2018-09-18
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US20180166143A1
公开(公告)日:2018-06-14
申请号:US15493964
申请日:2017-04-21
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
CPC分类号: G11C17/18 , G11C7/24 , G11C17/16 , H01L27/0251
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US10109366B2
公开(公告)日:2018-10-23
申请号:US15493964
申请日:2017-04-21
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US10109365B2
公开(公告)日:2018-10-23
申请号:US15492156
申请日:2017-04-20
发明人: Yuhsiang Chen , Shao-Yu Chou , Yu-Der Chih
摘要: A word line driver comprising a select word line level shifter configured to generate at least one output signal in the first voltage domain or a second voltage domain and a control word line level shifter coupled to the select word line level shifter and configured to generate at least one output signal in the second voltage domain or a third voltage domain based, at least in part, on the at least one output signal generated by the select word line level shifter.
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公开(公告)号:US20180151239A1
公开(公告)日:2018-05-31
申请号:US15492156
申请日:2017-04-20
发明人: Yuhsiang Chen , Shao-Yu Chou , Yu-Der Chih
IPC分类号: G11C17/18
CPC分类号: G11C17/18 , G11C8/08 , H03K3/012 , H03K3/356113 , H03K3/35613 , H03K3/356182
摘要: A word line driver comprising a select word line level shifter configured to generate at least one output signal in the first voltage domain or a second voltage domain and a control word line level shifter coupled to the select word line level shifter and configured to generate at least one output signal in the second voltage domain or a third voltage domain based, at least in part, on the at least one output signal generated by the select word line level shifter.
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公开(公告)号:US20210343354A1
公开(公告)日:2021-11-04
申请号:US17378923
申请日:2021-07-19
发明人: Meng-Sheng Chang , Chia-En Huang , Shao-Yu Chou , Yih Wang
IPC分类号: G11C17/16 , H01L23/528 , H01L27/112 , G11C17/18 , H01L23/525
摘要: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
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公开(公告)号:US20200227126A1
公开(公告)日:2020-07-16
申请号:US16830429
申请日:2020-03-26
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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