System and method for reducing cell area and current leakage in anti-fuse cell array

    公开(公告)号:US11437386B2

    公开(公告)日:2022-09-06

    申请号:US16786499

    申请日:2020-02-10

    摘要: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

    Word line driver
    7.
    发明授权

    公开(公告)号:US10109365B2

    公开(公告)日:2018-10-23

    申请号:US15492156

    申请日:2017-04-20

    IPC分类号: G11C8/00 G11C17/18

    摘要: A word line driver comprising a select word line level shifter configured to generate at least one output signal in the first voltage domain or a second voltage domain and a control word line level shifter coupled to the select word line level shifter and configured to generate at least one output signal in the second voltage domain or a third voltage domain based, at least in part, on the at least one output signal generated by the select word line level shifter.