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公开(公告)号：US20230376273A1
公开(公告)日：2023-11-23
申请号：US17749204
申请日：2022-05-20
Inventor： Rawan Naous , Kerem Akarvardar , Hidehiro Fujiwara , Haruki Mori , Mahmut Sinangil , Yu-Der Chih
CPC classification number: G06F7/5275 , G06F7/508 , G06F7/5443 , H03K19/20
Abstract: A compute-in-memory device may include a Booth encoder configured to receive at least one input of first bits, a Booth decoder configured to receive at least one weight of second bits and to output a plurality of partial products of the at least one input and the at least one weight, an adder configured to add a first partial product of the plurality of the partial products and a second partial product of the plurality of partial products before the Booth decoder generates a third partial product of the plurality of the partial products and to generate a plurality of sums of partial products, and a carry-lookahead adder configured to add the plurality of sums of partial products and to generate a final sum.
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公开(公告)号：US20220358013A1
公开(公告)日：2022-11-10
申请号：US17873262
申请日：2022-07-26
Inventor： Yu-Der Chih , Ching-Huang Wang , Yi-Chun Shih , Meng-Chun Shih , C. Y. Wang
Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
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公开(公告)号：US10936413B2
公开(公告)日：2021-03-02
申请号：US16295194
申请日：2019-03-07
Inventor： Yu-Der Chih , Ching-Huang Wang , Yi-Chun Shih , Meng-Chun Shih , C.Y. Wang
IPC: G06F11/10 , G11C17/16 , G11C17/18 , G11C29/44 , G11C29/50 , G11C29/56 , G11C29/00 , G06F3/06 , G11C29/04
Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
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公开(公告)号：US20190252032A1
公开(公告)日：2019-08-15
申请号：US16392741
申请日：2019-04-24
Inventor： Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
CPC classification number: G11C17/18 , G11C7/24 , G11C17/16 , H01L27/0251
Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号：US20180315464A1
公开(公告)日：2018-11-01
申请号：US15581097
申请日：2017-04-28
Inventor： Yu-Der Chih , Chien-Ye Lee , Jenn-Jou Wu , Yi-Chieh Chiu , Yi-Chun Shih , William J. Gallagher
IPC: G11C11/16
CPC classification number: G11C11/1677 , G11C11/161 , G11C11/1673 , G11C11/1675
Abstract: A method for verifying a write operation in a memory cell (e.g., a non-volatile memory cell) that includes performing a first read operation of the memory cell to measure a first current associated with the memory cell and comparing the measured first current associated with the memory cell to a first predetermined threshold current to determine whether the write operation changed the state of the memory cell. If the measured first current associated with the memory cell indicates the write operation did change the state of the memory cell the method further includes performing a second read operation of the memory cell to measure a second current associated with the memory cell and comparing the measured second current associated with the memory cell to a second predetermined threshold current to determine whether the write operation changed the state of the memory cell to the desired state or an intermediate state.
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Patent Agency Ranking
公开(公告)号：US11755410B2
公开(公告)日：2023-09-12
申请号：US17873262
申请日：2022-07-26
Inventor： Yu-Der Chih , Ching-Huang Wang , Yi-Chun Shih , Meng-Chun Shih , C. Y. Wang
IPC: G06F11/10 , G11C17/16 , G11C29/44 , G11C29/50 , G11C29/56 , G11C29/00 , G06F3/06 , G11C29/04 , G11C17/18
CPC classification number: G06F11/1068 , G06F3/064 , G06F3/0619 , G06F3/0638 , G06F3/0685 , G06F11/1048 , G11C17/16 , G11C17/18 , G11C29/44 , G11C29/50016 , G11C29/56004 , G11C29/78 , G11C2029/0403 , G11C2029/4402 , G11C2029/5002
Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
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公开(公告)号：US11211142B2
公开(公告)日：2021-12-28
申请号：US16829149
申请日：2020-03-25
Inventor： Yi-Chun Shih , Po-Hao Lee , Chia-Fu Lee , Yu-Der Chih , Yu-Lin Chen
Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.
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公开(公告)号：US20200227126A1
公开(公告)日：2020-07-16
申请号：US16830429
申请日：2020-03-26
Inventor： Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号：US10228998B2
公开(公告)日：2019-03-12
申请号：US15228294
申请日：2016-08-04
Inventor： Yu-Der Chih , Ching-Huang Wang , Yi-Chun Shih , Meng-Chun Shih , C. Y. Wang
IPC: G06F11/10 , G11C29/52 , G11C17/18 , G06F3/06 , G11C17/16 , G11C29/44 , G11C29/50 , G11C29/56 , G11C29/00 , G11C29/04
Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
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公开(公告)号：US20190035487A1
公开(公告)日：2019-01-31
申请号：US16044621
申请日：2018-07-25
Inventor： Yi-Chun Shih , Po-Hao Lee , Chia-Fu Lee , Yu-Der Chih , Yu-Lin Chen
Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.
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