公开(公告)号：US20130299917A1

公开(公告)日：2013-11-14

申请号：US13940888

申请日：2013-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lie-Yong Yang ,  Feng-Ming Chang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11 ,  H01L27/1104

Abstract: An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.

Abstract translation: 实施例是用于形成静态随机存取存储器（SRAM）单元的方法。 该方法包括在半导体衬底上形成晶体管并形成第一线性小区内连接和第二线性小区内连接。 晶体管的有源区的纵轴是平行的。 第一下拉晶体管和第一上拉晶体管共享第一公共栅极结构，并且第二下拉晶体管和第二上拉晶体管共享第二公共栅极结构。 第一线性单元间连接将第一下拉晶体管和第一上拉晶体管的有源区域电耦合到第二公共栅极结构。 第二线性单元间连接将第二下拉晶体管和第二上拉晶体管的有源区域电耦合到第一公共栅极结构。

公开(公告)号：US12080602B2

公开(公告)日：2024-09-03

申请号：US18331326

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.

Inventor： Wen-Chun Keng ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/08

CPC classification number: H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0847

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure and a second fin structure over the substrate. A top surface of the first fin structure and a top surface of the second fin structure are at different height levels. The semiconductor device structure also includes a first semiconductor element on the first fin structure and a second semiconductor element on the second fin structure. The first semiconductor element is wider than the second semiconductor element, and the first semiconductor element is closer to the substrate than the second semiconductor element.

公开(公告)号：US11710663B2

公开(公告)日：2023-07-25

申请号：US17194910

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.

Inventor： Wen-Chun Keng ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L21/311 ,  H01L21/3065

CPC classification number: H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0847

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first fin structure, a second fin structure, and a third fin structure over the semiconductor substrate. The semiconductor device structure also includes a merged semiconductor element on the first fin structure and the second fin structure and an isolated semiconductor element on the third fin structure. The semiconductor device structure further includes an isolation feature over the semiconductor substrate and partially or completely surrounding the first fin structure, the second fin structure, and the third fin structure. A top surface of the first fin structure is below a top surface of the isolation feature, and a top surface of the third fin structure is above the top surface of the isolation feature.

公开(公告)号：US12057505B2

公开(公告)日：2024-08-06

申请号：US17367497

申请日：2021-07-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0228 ,  H01L21/3083 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first well region and a second well region and a first fin structure formed in a first region of the first well region. The semiconductor device structure also includes a second fin structure formed in a second region of the first well region. In addition, the second fin structure is narrower than the first fin structure. The semiconductor device structure also includes a third fin structure formed in a first region of the second well region. In addition, a sidewall of the first fin structure is substantially aligned with a sidewall of the third fin structure.

公开(公告)号：US08766376B2

公开(公告)日：2014-07-01

申请号：US13940888

申请日：2013-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lie-Yong Yang ,  Feng-Ming Chang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11 ,  H01L27/1104

Abstract: An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.

Abstract translation: 实施例是用于形成静态随机存取存储器（SRAM）单元的方法。 该方法包括在半导体衬底上形成晶体管并形成第一线性小区内连接和第二线性小区内连接。 晶体管的有源区的纵轴是平行的。 第一下拉晶体管和第一上拉晶体管共享第一公共栅极结构，并且第二下拉晶体管和第二上拉晶体管共享第二公共栅极结构。 第一线性单元间连接将第一下拉晶体管和第一上拉晶体管的有源区域电耦合到第二公共栅极结构。 第二线性单元间连接将第二下拉晶体管和第二上拉晶体管的有源区域电耦合到第一公共栅极结构。