公开(公告)号：US11068638B2

公开(公告)日：2021-07-20

申请号：US16875060

申请日：2020-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiranmay Biswas ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/392 ,  H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  G06F30/394 ,  G06F119/06

Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.

公开(公告)号：US20190108304A1

公开(公告)日：2019-04-11

申请号：US16205441

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

IPC: G06F17/50 ,  H03K5/15 ,  H01L23/528

Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.

公开(公告)号：US10157258B2

公开(公告)日：2018-12-18

申请号：US15355410

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen Lin ,  Ming-Hsien Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F17/50

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

公开(公告)号：US10120971B2

公开(公告)日：2018-11-06

申请号：US15250934

申请日：2016-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lo ,  Chin-Chou Liu ,  Kuo-Nan Yang ,  Yu-Jen Chang

IPC: H01L23/48 ,  G06F17/50 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

公开(公告)号：US09852989B1

公开(公告)日：2017-12-26

申请号：US15397036

申请日：2017-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen Lin ,  Min-Yuan Tsai ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226

Abstract: Power grids of an IC are provided. A power grid includes first power traces disposed in a first metal layer and parallel to a first direction, second power traces disposed in a second metal layer and parallel to a second direction that is perpendicular to the first direction, and third power traces disposed in the first metal layer parallel to the first direction. The first power traces arranged in the same straight line are separated from each other by a plurality of first gaps. The third power traces arranged in the same straight line are separated from each other by a plurality of second gaps. Each first gap is surrounded by the two adjacent third power traces. Each second gap is surrounded by the two adjacent first power traces. The first power traces are coupled to the third power traces via the second power traces.

公开(公告)号：US09152751B2

公开(公告)日：2015-10-06

申请号：US14267537

申请日：2014-05-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Shen Lin ,  Jerry Chang-Jui Kao ,  Nitesh Katta ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Kuo-Nan Yang

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.

Abstract translation: 公开了一种包括以下概述的操作的方法。 基于在半导体器件的至少一个设计文件中的金属线的金属部分的波形周期内具有多个峰值的电流的波形函数来确定最大峰值的有效电流脉冲宽度，以计算半导体器件的至少一个设计文件中的占空比 有效电流脉冲宽度和波形周期。 根据金属段的物理特性确定金属段的最大直流极限。 根据最大直流限制和占空比函数之间的比例来确定交流电流（AC EM）电流限制。 当电流的最大峰值不超过AC EM电流限制时，金属部分包括在至少一个设计文件中的物理特性。

公开(公告)号：US20150091543A1

公开(公告)日：2015-04-02

申请号：US14296042

申请日：2014-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jerry Chang-Jui KAO ,  Chien-Ju Chao ,  Chin-Shen Lin ,  Nitesh Katta ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H03K17/56

CPC classification number: H03K19/0013 ,  H02M3/155 ,  H02M3/156 ,  H02M3/157 ,  H02M2001/0012

Abstract: A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data.

Abstract translation: 公开了包括多个电压控制电路和控制模块的电路。 每个电压控制电路由控制信号控制。 控制模块被配置为产生控制信号并且根据电压控制电路的当前处理转角条件和第一预定数据和第二预定数据中的至少一个来确定控制信号的电压电平或脉冲宽度。

公开(公告)号：US11908853B2

公开(公告)日：2024-02-20

申请号：US18069887

申请日：2022-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan Chang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Sheng-Fong Chen ,  Po-Hsiang Huang ,  Hiranmay Biswas ,  Sheng-Hsiung Chen ,  Aftab Alam Khan

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

CPC classification number: H01L27/0207 ,  G06F30/394 ,  H01L23/5226 ,  H01L27/11807 ,  H01L2027/11881

Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.

公开(公告)号：US10672709B2

公开(公告)日：2020-06-02

申请号：US15651165

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiranmay Biswas ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/394 ,  H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  G06F30/392 ,  G06F119/06

Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer and parallel to the first power lines, a plurality of third power lines formed in a second metal layer, and a plurality of fourth power lines formed in the second metal layer and parallel to the third power lines. The first and second power lines are interlaced in the first metal layer. The third and fourth power lines are interlaced in the second metal layer. Distances from the individual first power line to the two adjacent second power lines are the same, and distances from the individual third power line to the two adjacent fourth power lines are different.

公开(公告)号：US20150095873A1

公开(公告)日：2015-04-02

申请号：US14267537

申请日：2014-05-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Shen Lin ,  Jerry Chang-Jui Kao ,  Nitesh Katta ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Kuo-Nan Yang

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.

Abstract translation: 公开了一种包括以下概述的操作的方法。 基于在半导体器件的至少一个设计文件中的金属线的金属部分的波形周期内具有多个峰值的电流的波形函数来确定最大峰值的有效电流脉冲宽度，以计算半导体器件的至少一个设计文件中的占空比 有效电流脉冲宽度和波形周期。 根据金属段的物理特性确定金属段的最大直流极限。 根据最大直流限制和占空比函数之间的比例来确定交流电流（AC EM）电流限制。 当电流的最大峰值不超过AC EM电流限制时，金属部分包括在至少一个设计文件中的物理特性。