公开(公告)号：US20180060479A1

公开(公告)日：2018-03-01

申请号：US15250934

申请日：2016-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lo ,  Chin-Chou Liu ,  Kuo-Nan Yang ,  Yu-Jen Chang

IPC: G06F17/50 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/82 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14515 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/29099

Abstract: An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

公开(公告)号：US10553481B2

公开(公告)日：2020-02-04

申请号：US15692212

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Chang ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

公开(公告)号：US20190067093A1

公开(公告)日：2019-02-28

申请号：US15692212

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Chang ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

公开(公告)号：US10120971B2

公开(公告)日：2018-11-06

申请号：US15250934

申请日：2016-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lo ,  Chin-Chou Liu ,  Kuo-Nan Yang ,  Yu-Jen Chang

IPC: H01L23/48 ,  G06F17/50 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

公开(公告)号：US11908735B2

公开(公告)日：2024-02-20

申请号：US17815839

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Chang ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/485

CPC classification number: H01L21/76846 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53266 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/532 ,  H01L23/53295

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

公开(公告)号：US20220375790A1

公开(公告)日：2022-11-24

申请号：US17815839

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Chang ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.