公开(公告)号：US6069055A

公开(公告)日：2000-05-30

申请号：US886859

申请日：1997-07-01

申请人： Takaaki Ukeda ,  Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Masatoshi Arai ,  Masaru Moriwaki

发明人： Takaaki Ukeda ,  Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Masatoshi Arai ,  Masaru Moriwaki

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76232

摘要： The fabricating method for semiconductor devices in which the trench technique is employed to perform isolation between devices, and which comprises the steps of sequentially depositing a first film 2, 3 and a second film 4 on top of a silicon substrate 1, forming an element isolation trench 5 in the silicon substrate 1 with masking of the first film 2, 3 and second film 4 which have undergone patterning, and growing a silicon oxide film 6 that is generated by reaction of ozone and tetra-ethyl-ortho-silicate inside the element isolation trench where silicon is exposed.

摘要翻译： 采用沟槽技术来进行器件之间的隔离的半导体器件的制造方法，其包括以下步骤：在硅衬底1的顶部依次沉积第一膜2,3和第二膜4，形成元件隔离 硅衬底1中的沟槽5，其具有被图案化的第一膜2,3和第二膜4的掩蔽，并且通过在元件内的臭氧和四乙基原硅酸盐的反应产生氧化硅膜6 硅暴露的隔离沟槽。

公开(公告)号：US6034416A

公开(公告)日：2000-03-07

申请号：US61071

申请日：1998-04-16

申请人： Takashi Uehara ,  Toshiki Yabu ,  Mizuki Segawa ,  Takaaki Ukeda ,  Masatoshi Arai ,  Masaru Moriwaki

发明人： Takashi Uehara ,  Toshiki Yabu ,  Mizuki Segawa ,  Takaaki Ukeda ,  Masatoshi Arai ,  Masaru Moriwaki

IPC分类号： H01L21/8247 ,  H01L29/72

CPC分类号： H01L27/11526 ,  H01L27/11539

摘要： The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions. In a flash-integrated logic LSI incorporating a nonvolatile memory cell, a density can be increased in the memory cell region and the peripheral circuit region and the costs can be reduced.

摘要翻译： 外围电路区域中的衬底的顶表面处于比存储单元区域中的衬底顶表面高的位置，并且基本上等于浮栅电极的顶表面。 通过栅极绝缘膜在浮栅上形成控制栅电极，通过栅极绝缘膜在外围电路区域的基板上形成栅电极。 如果控制栅电极由多层膜形成，用于沟槽隔离的掩埋绝缘膜的顶表面可以处于等于浮栅电极的顶表面或底层膜的顶表面的水平。 可以减小存储单元区域中的控制栅电极与外围电路区域中的栅电极之间的电平差，从而可以在这些区域中形成精细图案。 在包含非易失性存储单元的闪存集成逻辑LSI中，可以在存储单元区域和外围电路区域中增加密度，并且可以降低成本。

公开(公告)号：US20050102363A1

公开(公告)日：2005-05-12

申请号：US10983759

申请日：2004-11-09

申请人： Makoto Yokomura ,  Takashi Hayashi ,  Takashi Satomura ,  Toshiro Mitamura ,  Rika Aizawa ,  Masaru Moriwaki ,  Soichiro Fujioka ,  Minoru Hirano ,  Yuichiro Hara

发明人： Makoto Yokomura ,  Takashi Hayashi ,  Takashi Satomura ,  Toshiro Mitamura ,  Rika Aizawa ,  Masaru Moriwaki ,  Soichiro Fujioka ,  Minoru Hirano ,  Yuichiro Hara

IPC分类号： G06F13/00 ,  G06F15/16 ,  H04L12/58

CPC分类号： G06Q10/107 ,  H04L51/14

摘要： An E-mail transmission control device comprises: a mail information storage unit; a destination information storage unit; an E-mail transmission unit; an error information reception unit for receiving error information; an error information decision unit for deciding whether or not the error information satisfies a predetermined condition; a destination excluding unit for executing the destination indicated by the destination information owned by the error information, from the candidates of the destination, in case the error information decision unit decides the satisfaction of the predetermined condition. The electronic transmission control device further comprises a re-transmission decision unit for deciding whether or not a predetermined condition is satisfied, after the destination excluding unit performed the exclusion. The E-mail transmission unit transmits the E-mail to the excluded destination in case the re-transmission decision unit decides the satisfaction of the predetermined condition.

摘要翻译： 电子邮件传输控制装置包括：邮件信息存储单元; 目的地信息存储单元; 电子邮件传输单元; 用于接收错误信息的错误信息接收单元; 错误信息决定单元，用于判定所述错误信息是否满足预定条件; 在所述错误信息决定单元判定所述预定条件的满足的情况下，从所述目的地的候选者执行由所述错误信息所拥有的目的地信息表示的目的地的目的地排除单元。 电子传输控制装置还包括在目的地排除单元执行排除之后，决定是否满足预定条件的重传决定单元。 电子邮件发送单元在重新发送决定单元决定预定条件的满足的情况下，将电子邮件发送到排除目的地。

公开(公告)号：US06563178B2

公开(公告)日：2003-05-13

申请号：US09818550

申请日：2001-03-28

申请人： Masaru Moriwaki ,  Takayuki Yamada

发明人： Masaru Moriwaki ,  Takayuki Yamada

IPC分类号： H01L2994

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： A first gate electrode for an n-channel MOSFET includes first and second metal films and a low-resistivity metal film. The first metal film has been deposited on a first gate insulating film and is made of a first metal having a work function located closer to the conduction band of silicon with reference to an intermediate level of silicon bandgap. The second metal film has been deposited on the first metal film and is made of a second metal having a work function located closer to the valence band of silicon with reference to the intermediate level of silicon bandgap. The low-resistivity metal film has been deposited on the second metal film. A second gate electrode for a p-channel MOSFET includes: the second metal film, which has been deposited on a second gate insulating film and is made of the second metal; and the low-resistivity metal film deposited on the second metal film.

摘要翻译： 用于n沟道MOSFET的第一栅电极包括第一和第二金属膜和低电阻率金属膜。 第一金属膜已经沉积在第一栅极绝缘膜上，并且相对于硅带隙的中间水平，由具有更靠近硅的导带的功函数的第一金属制成。 第二金属膜已经沉积在第一金属膜上，并且相对于硅带隙的中间水平，由具有位于更接近硅的价带的功函数的第二金属制成。 低电阻率金属膜已沉积在第二金属膜上。 用于p沟道MOSFET的第二栅电极包括：已经沉积在第二栅绝缘膜上并由第二金属制成的第二金属膜; 以及沉积在第二金属膜上的低电阻率金属膜。

公开(公告)号：US06812101B2

公开(公告)日：2004-11-02

申请号：US10332519

申请日：2003-01-10

申请人： Masaru Moriwaki ,  Masaaki Niwa ,  Masafumi Kubota

发明人： Masaru Moriwaki ,  Masaaki Niwa ,  Masafumi Kubota

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/28185 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/823462 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/517

摘要： A zirconium silicate layer 103 is formed on a silicon substrate 100, a zirconium oxide layer 102 is also formed on the zirconium silicate layer 103, and the zirconium oxide layer 102 is then removed, thereby forming a gate insulating film 104 made of the zirconium silicate layer 103.

摘要翻译： 在硅衬底100上形成硅酸锆层103，在硅酸锆层103上也形成氧化锆层102，然后除去氧化锆层102，从而形成由硅酸锆制成的栅绝缘膜104 层103。

公开(公告)号：US06548389B2

公开(公告)日：2003-04-15

申请号：US09759451

申请日：2001-01-16

申请人： Masaru Moriwaki ,  Takayuki Yamada ,  Kazuhiko Yamamoto

发明人： Masaru Moriwaki ,  Takayuki Yamada ,  Kazuhiko Yamamoto

IPC分类号： H01L213205

CPC分类号： H01L27/0629 ,  H01L21/28088

摘要： After an insulating film serving as a gate insulating film is formed on a semiconductor substrate, a titanium nitride film is deposited by chemical vapor deposition on the insulating film. Then, a tungsten film is deposited by sputtering on the titanium nitride film. Subsequently, a multilayer film composed of the tungsten film and the titanium nitride film is patterned to form a gate electrode composed of the multilayer film.

公开(公告)号：US06514883B2

公开(公告)日：2003-02-04

申请号：US09956554

申请日：2001-09-20

申请人： Masaru Moriwaki ,  Takayuki Yamada

发明人： Masaru Moriwaki ,  Takayuki Yamada

IPC分类号： H01L2131

CPC分类号： H01L29/513 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517

摘要： A metal target, at least the surface region of which has been oxidized, is prepared in a chamber. Then, a sputtering process is performed on the metal target with an inert gas ambient created in the chamber, thereby depositing a first metal oxide film as a lower part of a gate insulating film over a semiconductor substrate. Next, a reactive sputtering process is performed on the metal target with a mixed gas ambient, containing the inert gas and an oxygen gas, created in the chamber, thereby depositing a second metal oxide film as a middle or upper part of the gate insulating film over the first metal oxide film.

摘要翻译： 至少其表面区域被氧化的金属靶在室中制备。 然后，在室内产生的惰性气体环境对金属靶进行溅射处理，由此在半导体衬底上沉积作为栅极绝缘膜的下部的第一金属氧化物膜。 接下来，在室内形成含有惰性气体和氧气的混合气体环境下对金属靶进行反应性溅射处理，由此沉积作为栅极绝缘膜的中间或上部的第二金属氧化物膜 超过第一金属氧化物膜。

公开(公告)号：US06740941B2

公开(公告)日：2004-05-25

申请号：US10323636

申请日：2002-12-20

申请人： Masaru Moriwaki ,  Takayuki Yamada

发明人： Masaru Moriwaki ,  Takayuki Yamada

IPC分类号： H01L2994

CPC分类号： H01L29/513 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517

摘要： A metal target, at least the surface region of which has been oxidized, is prepared in a chamber. Then, a sputtering process is performed on the metal target with an inert gas ambient created in the chamber, thereby depositing a first metal oxide film as a lower part of a gate insulating film over a semiconductor substrate. Next, a reactive sputtering process is performed on the metal target with a mixed gas ambient, containing the inert gas and an oxygen gas, created in the chamber, thereby depositing a second metal oxide film as a middle or upper part of the gate insulating film over the first metal oxide film.

摘要翻译： 至少其表面区域被氧化的金属靶在室中制备。 然后，在室内产生的惰性气体环境对金属靶进行溅射处理，由此在半导体衬底上沉积作为栅极绝缘膜的下部的第一金属氧化物膜。 接下来，在室内形成含有惰性气体和氧气的混合气体环境下对金属靶进行反应性溅射处理，由此沉积作为栅极绝缘膜的中间或上部的第二金属氧化物膜 超过第一金属氧化物膜。

公开(公告)号：US06462386B2

公开(公告)日：2002-10-08

申请号：US09854468

申请日：2001-05-15

申请人： Masaru Moriwaki ,  Takayuki Yamada

发明人： Masaru Moriwaki ,  Takayuki Yamada

IPC分类号： H01L21441

CPC分类号： H01L27/11526 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11539 ,  H01L29/66545

摘要： A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon film formed on the first gate insulating film. The second MOSFET includes a second gate insulating film formed on the semiconductor substrate and having a relatively small thickness and a second gate electrode composed of a metal film made of a refractory metal or a compound of a refractory metal and formed on the second gate insulating film.

摘要翻译： 半导体器件包括第一MOSFET和第二MOSFET。 第一MOSFET包括形成在半导体衬底上并且具有相对较大厚度的第一栅极绝缘膜和由形成在第一栅极绝缘膜上的多晶硅膜构成的第一栅电极。 第二MOSFET包括形成在半导体衬底上并且具有相对较小厚度的第二栅极绝缘膜和由难熔金属或难熔金属化合物制成的金属膜构成的第二栅极，并形成在第二栅极绝缘膜上 。

公开(公告)号：US06445047B1

公开(公告)日：2002-09-03

申请号：US09695381

申请日：2000-10-25

申请人： Takayuki Yamada ,  Masaru Moriwaki

发明人： Takayuki Yamada ,  Masaru Moriwaki

IPC分类号： H01L2976

CPC分类号： H01L21/82345 ,  H01L29/495 ,  H01L29/4966

摘要： A semiconductor device includes: a first-surface-channel-type MOSFET having a first threshold voltage; and a second-surface-channel-type MOSFET with a second threshold voltage having an absolute value greater than an absolute value of said first threshold voltage. The first-surface-channel-type MOSFET includes: a first gate insulating film formed on a semiconductor substrate; and a first gate electrode, which has been formed out of a poly-silicon film over the first gate insulating film. The second-surface-channel-type MOSFET includes: a second gate insulating film formed on the semiconductor substrate; and a second gate electrode, which has been formed out of a refractory metal film over the second gate insulating film. The refractory metal film is made of a refractory metal or a compound thereof.

摘要翻译： 半导体器件包括：具有第一阈值电压的第一表面沟道型MOSFET; 以及具有绝对值大于所述第一阈值电压的绝对值的第二阈值电压的第二表面沟道型MOSFET。 第一表面沟道型MOSFET包括：形成在半导体衬底上的第一栅极绝缘膜; 以及在第一栅极绝缘膜上形成的由多晶硅膜形成的第一栅电极。 所述第二表面沟道型MOSFET包括：形成在所述半导体衬底上的第二栅极绝缘膜; 以及在所述第二栅极绝缘膜上形成的难熔金属膜之外的第二栅电极。 难熔金属膜由难熔金属或其化合物制成。