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    Method of arbitration for bus use request and system therefor
    1.
    发明授权
    Method of arbitration for bus use request and system therefor 失效
    总线使用请求仲裁方法及其系统

    公开(公告)号：US07380034B2

    公开(公告)日：2008-05-27

    申请号：US11110667

    申请日：2005-04-21

    申请人： Takafumi Fujiwara ,  Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    发明人： Takafumi Fujiwara ,  Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    IPC分类号： G06F13/00

    CPC分类号： G06F13/3625 ,  G06F13/364

    摘要： In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

    摘要翻译： 在连接到总线的多个主设备中，当需要使用总线时，主设备向仲裁器发出请求使用总线经过预定间隔的请求信号，而另一个主设备发出请求信号 仲裁器，当需要使用总线时，立即请求使用总线的请求信号。 仲裁器授权通过同样处理来自主设备的请求信号来使用总线的权利。 还准备了表示总线中的业务的信号，并且在高业务量的情况下经过间隔后发出请求信号，但是在流量低的情况下立即发出请求信号。 因此，可以详细地调整使用权的实际优先级，或者通过存在或不存在这样的间隔或其长度来动态地改变这种优先级。

    Image input/output control system
    2.
    发明授权
    Image input/output control system 有权
    图像输入/输出控制系统

    公开(公告)号：US06707569B1

    公开(公告)日：2004-03-16

    申请号：US09435905

    申请日：1999-11-08

    申请人： Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda ,  Takafumi Fujiwara

    发明人： Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda ,  Takafumi Fujiwara

    IPC分类号： G06F1500

    CPC分类号： H04N1/32443 ,  H04N1/00236 ,  H04N1/32358 ,  H04N2201/002 ,  H04N2201/0034 ,  H04N2201/0081 ,  H04N2201/0082

    摘要： A scanner is connected to a G bus and a B bus by way of a scanner controller and a G bus/B bus interface (GBI). A printer is connected in a similar manner. Furthermore, the scanner controller is connected directly to a printer controller with a CP bus. The GBI is capable of performing DMA transfer and data can be transferred between the GBIs. Furthermore, data can be transferred by way of the G bus and a RAM or the B bus and the RAM. The GBI is connected to the scanner controller and the printer controller by way of FIFOs, respectively. Accordingly, an image input/output control system according to the present invention is capable of absorbing differences in data transfer speeds and can be connected to various kinds of scanners and printers.

    摘要翻译： 扫描仪通过扫描仪控制器和G总线/ B总线接口（GBI）连接到G总线和B总线。 打印机以类似的方式连接。 此外，扫描仪控制器直接连接到具有CP总线的打印机控制器。 GBI能够执行DMA传输，数据可以在GBI之间传输。 此外，数据可以通过G总线和RAM或B总线和RAM进行传输。 GBI分别通过FIFO连接到扫描仪控制器和打印机控制器。 因此，根据本发明的图像输入/输出控制系统能够吸收数据传送速度的差异，并且可以连接到各种扫描仪和打印机。

    Bus management using logic-based arbitration among bus access requests
    4.
    发明授权
    Bus management using logic-based arbitration among bus access requests 失效
    总线访问请求中使用基于逻辑的仲裁的总线管理

    公开(公告)号：US06438635B1

    公开(公告)日：2002-08-20

    申请号：US09122012

    申请日：1998-07-24

    申请人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    发明人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    IPC分类号： G06F1336

    CPC分类号： G06F13/364

    摘要： A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

    摘要翻译： 来自CPU的AP总线，来自系统存储器的MC总线，连接有输入/输出设备的IO总线和用于传送扫描器/打印机控制器的图像数据的G总线连接到系统总线桥（ SBB）。 SBB根据主机的请求，将任何一个P总线，G总线和IO总线作为主机和任何一个MC总线和IO总线作为从机连接。 此时，P总线和IO总线可以与G总线和MC总线并联连接。 因此，可以使用CPU的输入/输出设备并行地执行扫描器/打印机控制器对存储器的访问。 这使得可以有效地处理诸如图像数据的大量数据。

    Bus control apparatus
    5.
    发明授权
    Bus control apparatus 失效
    总线控制装置

    公开(公告)号：US06708236B1

    公开(公告)日：2004-03-16

    申请号：US09492518

    申请日：2000-01-27

    申请人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    发明人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    IPC分类号： G06F1300

    CPC分类号： H04N1/0083 ,  H04N1/32561 ,  H04N1/32593 ,  H04N1/32603 ,  H04N2201/0091 ,  H04N2201/0093

    摘要： Bus control apparatus solves the problem that a high-speed bus which supports only burst transfer cannot be used when the boundary of a transfer memory address is not coincident with a unit boundary. A scanner controller and printer controller connected to a G bus capable of performing only burst transfer and a B bus capable of performing even single transfer determine from the address and data length of data to be transferred whether the data does not match the memory boundary. If the data does not match this boundary, a data portion which is not accommodated within the burst transfer unit is single-transferred using the B bus. A data portion which is accommodated within the burst transfer unit is burst-transferred using the G bus.

    摘要翻译： 总线控制装置解决了当传输存储器地址的边界与单位边界不一致时不能使用仅支持突发传输的高速总线的问题。 连接到能够执行突发传输的G总线的扫描器控制器和打印机控制器以及能够执行甚至单次传输的B总线根据要传送的数据的地址和数据长度确定数据是否与存储器边界不匹配。 如果数据与该边界不匹配，则使用B总线单独传送不容纳在突发传送单元内的数据部分。 使用G总线突发传送容纳在突发传送单元内的数据部分。

    Memory management for use with burst mode
    6.
    发明授权
    Memory management for use with burst mode 失效
    内存管理用于突发模式

    公开(公告)号：US06499076B2

    公开(公告)日：2002-12-24

    申请号：US09917715

    申请日：2001-07-31

    申请人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    发明人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    IPC分类号： G06F100

    CPC分类号： G06F13/364

    摘要： A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

    摘要翻译： 来自CPU的AP总线，来自系统存储器的MC总线，连接有输入/输出设备的IO总线和用于传送扫描器/打印机控制器的图像数据的G总线连接到系统总线桥（ SBB）。 SBB根据主机的请求，将任何一个P总线，G总线和IO总线作为主机和任何一个MC总线和IO总线作为从机连接。 此时，P总线和IO总线可以与G总线和MC总线并联连接。 因此，可以使用CPU的输入/输出设备并行地执行扫描器/打印机控制器对存储器的访问。 这使得可以有效地处理诸如图像数据的大量数据。

    Bus management based on bus status
    7.
    发明授权
    Bus management based on bus status 失效

    公开(公告)号：US07062664B2

    公开(公告)日：2006-06-13

    申请号：US09917833

    申请日：2001-07-31

    申请人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    发明人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    IPC分类号： G06F1/26 ,  G05D3/12

    CPC分类号： G06F13/364

    摘要： A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

    Method of delaying bus request signals to arbitrate for bus use and system therefor
    8.
    发明授权
    Method of delaying bus request signals to arbitrate for bus use and system therefor 失效
    延迟总线请求信号以仲裁总线使用的方法及其系统

    公开(公告)号：US06952747B2

    公开(公告)日：2005-10-04

    申请号：US10314285

    申请日：2002-12-09

    申请人： Takafumi Fujiwara ,  Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    发明人： Takafumi Fujiwara ,  Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    IPC分类号： G06F13/362 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/364 ,  G06F13/372

    CPC分类号： G06F13/3625 ,  G06F13/364

    摘要： In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

    摘要翻译： 在连接到总线的多个主设备中，当需要使用总线时，主设备向仲裁器发出请求使用总线经过预定间隔的请求信号，而另一个主设备发出请求信号 仲裁器，当需要使用总线时，立即请求使用总线的请求信号。 仲裁器授权通过同样处理来自主设备的请求信号来使用总线的权利。 还准备了表示总线中的业务的信号，并且在高业务量的情况下经过间隔后发出请求信号，但是在流量低的情况下立即发出请求信号。 因此，可以详细地调整使用权的实际优先级，或者通过存在或不存在这样的间隔或其长度来动态地改变这种优先级。

    Method of arbitration for bus use request and system therefor
    9.
    发明申请
    Method of arbitration for bus use request and system therefor 失效
    总线使用请求仲裁方法及其系统

    公开(公告)号：US20050188139A1

    公开(公告)日：2005-08-25

    申请号：US11110667

    申请日：2005-04-21

    申请人： Takafumi Fujiwara ,  Katsunori Kato ,  Noburo Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    发明人： Takafumi Fujiwara ,  Katsunori Kato ,  Noburo Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    IPC分类号： G06F13/362 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/364 ,  G06F13/372

    CPC分类号： G06F13/3625 ,  G06F13/364

    摘要： In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

    摘要翻译： 在连接到总线的多个主设备中，当需要使用总线时，主设备向仲裁器发出请求使用总线经过预定间隔的请求信号，而另一个主设备发出请求信号 仲裁器，当需要使用总线时，立即请求使用总线的请求信号。 仲裁器授权通过同样处理来自主设备的请求信号来使用总线的权利。 还准备了表示总线中的业务的信号，并且在高业务量的情况下经过间隔后发出请求信号，但是在流量低的情况下立即发出请求信号。 因此，可以详细地调整使用权的实际优先级，或者通过存在或不存在这样的间隔或其长度来动态地改变这种优先级。

    Memory control device having less power consumption for backup
    10.
    发明授权
    Memory control device having less power consumption for backup 有权
    内存控制设备具有较少的备用功耗

    公开(公告)号：US07388800B2

    公开(公告)日：2008-06-17

    申请号：US11179539

    申请日：2005-07-13

    申请人： Tadaaki Maeda

    发明人： Tadaaki Maeda

    IPC分类号： G11C5/01

    CPC分类号： G06F1/3275 ,  G06F1/30 ,  G06F1/3203 ,  G06F13/1668 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

    摘要： When it is detected that the voltage of a main power supply is reduced below a predetermined value during a normal operation, a power controller switches a power supply for a DRAM from the main power supply to a battery power supply and makes an instruction signal for instruction a self-refresh mode to a memory controller active. In response to this, the memory controller changes a clock enable signal for the DRAM to a low level to establish the self-refresh mode of the DRAM, and, after, the self-refresh mode of the DRAM is established, supplying of power to the memory controller is stopped. The clock enable signal for the DRAM is maintained to the low level by pull-down resistance even when the supplying of power to the memory controller is stopped from a condition that the signal is changed to the low level in the self-refresh mode, thereby maintaining the self-refresh mode of the DRAM.

    摘要翻译： 当在正常操作期间检测到主电源的电压被降低到低于预定值时，电源控制器将DRAM的电源从主电源切换到电池电源，并且产生用于指令的指令信号 一个自刷新模式到一个内存控制器激活。 响应于此，存储器控制器将用于DRAM的时钟使能信号改变为低电平以建立DRAM的自刷新模式，之后建立DRAM的自刷新模式，向 内存控制器停止。 即使当在自刷新模式中信号变为低电平的状态停止向存储器控制器供电时，DRAM的时钟使能信号也被下拉电阻维持在低电平，从而 保持DRAM的自刷新模式。